Chip packaging structure

Abstract

The invention discloses a chip packaging structure, comprising a first substrate, a chip, a second substrate, a plurality of conducting wires, a plurality of solder balls and a packaging colloid. The chip is configured on the first substrate. The second substrate is configured on the chip and is provided with an upper surface and a lower surface, wherein the height of the lower surface in relation to the chip is smaller than the height of the upper surface in relation to the chip, the upper surface is provided with a solder ball mounting surface and a conducting wire jointing surface, and the height between the conducting wire jointing surface and the first substrate is smaller than the height between the solder ball mounting surface and the first substrate. The conducting wire jointing surface is connected with the first substrate via these conducting wires. These solder balls are configured on the solder ball mounting surface. The packaging colloid is configured on the first substrate and covers the chip, the second substrate and these solder balls, and the packaging colloid is exposed out of the top surfaces of the solder balls.

Description

Technical field [0001] The present invention relates to a chip packaging structure, and in particular to a chip packaging structure suitable for package-on-package (POP). Background technique [0002] The purpose of chip packaging technology is to provide sufficient signal path, heat dissipation path and structural protection for the chip. The known technology proposes a package-on-package (POP) 3D packaging method, which can reduce the bearing area occupied by these chip packaging structures on the circuit board by stacking multiple chip packaging structures on each other. [0003] figure 1 A cross-sectional schematic diagram of a known chip package structure applicable to package stacking is shown. Please refer to figure 1 In the chip packaging structure 100, a chip 110 is disposed on a first substrate 120, and a second substrate 130 is disposed on the chip 110. The second substrate 130 is electrically connected to the first substrate 120 by a plurality of first wires 140, and ...

AI Technical Summary

Problems solved by technology

[0008] Moreover, during the process of reflowing these solder balls 160 to assemble the chip package structure 100 to another chip package structure (not shown), the heat-expanded encapsulant 170 will easily squeeze a part of these heat-melted solder balls 160 . out to the surface of the encapsulant 170 , thus causing an electrical short circuit between adjacent solder balls 160

Images