Equivalence verification method for eliminating misjudgment by combining constraint satisfaction

A technology of equivalence verification and constraint satisfaction, applied in the field of effective misjudgment elimination and cost-effectiveness verification, it can solve the problems of integrated circuit chip design scale growth and complex functions, so as to speed up time-to-market, improve success rate, and eliminate errors. the effect of judgment

Inactive Publication Date: 2010-11-17
JILIN UNIV
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Problems solved by technology

Due to the sharp increase in the design scale of integrated circuit chips and the increasingly complex functions, equivalence verification has become the main bottleneck of the design process

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  • Equivalence verification method for eliminating misjudgment by combining constraint satisfaction
  • Equivalence verification method for eliminating misjudgment by combining constraint satisfaction
  • Equivalence verification method for eliminating misjudgment by combining constraint satisfaction

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Embodiment Construction

[0036] Below by specific embodiment and accompanying drawing, the present invention is described in further detail:

[0037] see figure 1 and figure 2 , an equivalence verification method that combines constraint satisfaction and eliminates misjudgments, and its steps include at least:

[0038] Step 1: Establish a model for specification description and implementation description;

[0039] Step 2: Select the appropriate candidate equivalence pair positions in the specification model and the implementation model to facilitate the equivalence verification based on the cut set method;

[0040] Step 3: quickly solve the candidate equivalence pairs using a constraint solver;

[0041] Step 4: Judging whether there is a misjudgment: If the specification model and the implementation model are equivalent, the verification result is equivalent, and there is no misjudgment, go to step 6; if the specification model and the implementation model are not equivalent, but this time is not ...

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Abstract

The invention relates to an equivalence verification method for eliminating misjudgment by combining constraint satisfaction and belongs to the technical field of model verification. The method comprises the following steps of: selecting appropriate candidate equivalence pairs from a normative model and an implementation model according to heuristic information; performing boundary assignment-based constraint propagation rapid solving on an input variable of a circuit in a constraint solver; and directly inputting a result if a misjudgment phenomenon does not exist, and if the misjudgment exists, eliminating the misjudgment by the following steps of: a) converting a model corresponding to the current equivalence pair into a constraint relation; b) solving all non-equivalent assignments of the normative model and the implementation model by using the constraint solver and converting the assignments into a constraint relation; and c) calling the constraint solver to solve the constraint relations obtained by the step a) and the step b), judging that the two models are equivalent to each other if a result is unsatisfactory and judging that the models are non-equivalent if the result is satisfactory. Due to the adoption of the method, equivalence verification efficiency is improved, the first silicon slice success rate of a chip is enhanced and the time to market of an electronic product is shortened.

Description

technical field [0001] The patent of the present invention relates to an equivalence verification method combining constraint satisfaction and eliminating misjudgment, in particular to an effective misjudgment elimination method in the equivalence verification method, which belongs to the technical field of model verification. Background technique [0002] The research on model validation began in the early 1980s by Edmund M. Clarke, Allen Emerson and Joseph Sifakis from France proposed independently. In 1998, Bryant, Clarke, Emerson and McMillon received the Paris Kanellakis Award for Theory and Practice from the Association for Computing Machinery for their pioneering work in the field of model verification. In 2008, in view of the foundational contributions made by Clarke, Emerson and Sifakis in the field of model verification and making it a very effective verification technology widely used in industrial hardware and software, the three were simultaneously awarded the ...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 欧阳丹彤张立明白洪涛李占山
Owner JILIN UNIV
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