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Clock circuit for a digital circuit

A clock circuit, digital circuit technology, applied in the direction of generating/distributing signals, etc., can solve the problem of not allowing the power to be instantly reduced or increased, not allowing the effective monitoring of the link, etc.

Inactive Publication Date: 2010-11-24
ZARLINK SEMICON LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] A power-down mode is available in current devices, however, this does not allow effective monitoring of the link
Furthermore, recovery after power-down mode is not error-free, and further the power-down mode does not allow power to be reduced or increased instantaneously

Method used

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  • Clock circuit for a digital circuit
  • Clock circuit for a digital circuit
  • Clock circuit for a digital circuit

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Embodiment Construction

[0016] Embodiments of the present invention reduce power consumption by reducing clock speed when the digital circuitry is not operating at full capacity. The problem is that if this clock is interrupted or the clock rate changes, circuits or integrated circuits (ICs) that require an input clock cannot function properly unless they are designed to allow clock rate changes other than such changes, because they cannot accept changes in the clock rate. Sudden transitions in clock rate. Embodiments of the present invention allow ICs that are not specifically designed to accept clock rate variations to operate when the clock rates vary as described above. These circuits experience low throughput when the clock rate is reduced.

[0017] For example, a GE Ethernet PHY is expected to operate at an internal clock rate of 1GHz. The ICs above expect either a 25MHz or 125MHz input clock. Reducing the clock rate for the circuits described above reduces the power consumption, as well as ...

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PUM

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Abstract

A method of saving power in a digital circuit driven by a clock running at a rate R, comprising reducing said rate R to a lower rate R' during periods when said digital circuit is operating at a capacity less than its maximum capacity, and wherein the change from rate R to rate R' is carried out as a smooth transition.

Description

technical field [0001] The present invention relates to the generation of clock signals for digital circuits, in particular to clock circuits with a sleep mode, eg suitable for use in communication network equipment. Background technique [0002] Digital devices are driven by clock signals that control the sequence of operations within digital circuits. The power consumption of this digital part is related to the frequency of the clock signal. The higher the frequency of the clock, the higher the power consumption will be. As the world moves towards a hands-off environment, energy-efficient technologies are becoming more and more important in the field of communications. For example, the new IEEE 802.3 Ethernet standard calls for energy-efficient Ethernet. [0003] A power down mode is available in current devices, however, this does not allow effective monitoring of the link. Furthermore, recovery after power down mode is not error-free, and further the power down mode ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F1/08
CPCG06F1/08
Inventor 路易丝·戈兰马蒙·阿布·赛义多西尔瓦娜·贡萨拉·罗德里格斯
Owner ZARLINK SEMICON LTD