Method and device for computing error location polynomial in decoding through binary BCH (Bose-Chaudhuri-Hocquenghem) code
A technology for calculating errors and BCH codes, which is applied in the direction of data representation error detection/correction, using linear codes for error correction/detection, and using block codes for error correction/detection. Consumption and other issues to achieve the effect of saving calculation time, reducing power consumption, and reducing decoding delay
Inactive Publication Date: 2011-01-19
ALLWINNER TECH CO LTD
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However, with the increase of t in the current prior art serial device for realizing the non-inverted BM method, N is represented by t 2 As the base number increases, the speed of the BCH code decoder is more and more restricted by the calculation time of the device. As the error correction capability t is required to be higher and higher, this method greatly increases the BCH decoding delay, and also greatly increases The power consumption of the decoding circuit
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Abstract
The invention discloses a method and a device for computing an error location polynomial in decoding through a binary BCH (Bose-Chaudhuri-Hocquenghem) code. The method comprises the following steps of: (1) starting iteration from an even number according to a computed syndrome, initializing a step-length initial value i and computing the initial parameter of the error location polynomial; (2) computing the ith iterated error location polynomial and an i+2nd iterated correction term; (3) judging and computing the parameter of the next iterative computation; (4) setting the step length of value buil-up constant of i to be 2, i.e. i<=i+2; (5) comparing the value of iteration times with 2t-1, selecting to continue iteration according to a comparison result, and turning to the step (2), or ending the iteration and turning to a step (6) for processing; and (6) outputting the i-2nd iterated error location polynomial, and finishing the computation. The invention also greatly reduces the power consumption of a decoding circuit while reducing the binary BCH decoding delay.
Description
technical field The present invention relates to the technical field of binary BCH error correction code encoding and decoding, in particular to a method and device for calculating an error position polynomial in the decoding process of the binary BCH error correction code. Background technique BCH error correction code (also called BCH code) is a cyclic check code used for error correction, especially suitable for random error correction. Co-presented by R.C.Bose, D.K.Chaudhuri and A.Hocquenghem. It divides the information sequence to be sent by the source into message groups according to a fixed κ bit group, and then transforms each message group into a binary number group of n (n>κ) independently, which is called a code word. The process of converting a message group into a codeword is called encoding, and the inverse process is called decoding. The BCH code has a rigorous algebraic theory and is the most thoroughly studied type of code at present. It is the most co...
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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/15
Inventor 庞文玉彭刚匡双鸽
Owner ALLWINNER TECH CO LTD
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