Steady state phase-locking error-free phase locking system and phase locking method

A phase-locking error and phase-locking technology, which is applied to the phase-locking system and the field of phase-locking where the steady-state phase-locking error is zero, can solve problems such as difficult implementation and complex circuits.

Inactive Publication Date: 2011-03-16
江苏锦丰电子有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In order to achieve higher requirements, the circuit will become very complicated

Method used

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  • Steady state phase-locking error-free phase locking system and phase locking method
  • Steady state phase-locking error-free phase locking system and phase locking method
  • Steady state phase-locking error-free phase locking system and phase locking method

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Embodiment 1

[0070] 1. Set the frequency of the input signal X(t) as fx=250kHz, the amplitude as a, and the initial phase as φx. m=4, N=8, the input signal is divided into two routes, one to the phase-locked loop, and the other to the A / D conversion. After the first road is phase-locked, its output enters the 4 frequency multiplier, and 4fx=fs is obtained as the sampling signal;

[0071] 2. The A / D output is a digital signal sampled at 1MHz, which is transformed into a complex signal by "H" (Hilbert);

[0072] 3, utilize formula (3) to obtain N / m=2, promptly the output of No. 2 filter is:

[0073] F ( N / m ) = F ( 8 / 4 ) = F ( 2 ) = Σ n = 0 7 X ( ...

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PUM

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Abstract

The invention relates to a steady state phase-locking error-free phase locking system and a steady state phase-locking error-free phase locking method. In the method, the natural distribution law of center frequency of each sub-band filter is determined according to the sampling frequency (fs) and the number of sampling points (N) in fast Fourier transform (FFT); the bandwidth of the sub-band filter and the position of the center frequency can be changed by regulating the sampling frequency; when the sampling frequency fs is integral multiple of locked signal frequency fx, and the number of sampling points is N, a locked signal is certainly at the center frequency of a N/mth sub-band filter; and when the sampling frequency fs is determined by the locked signal frequency fx, the center of the N/mth sub-band filter is the position of the locked signal frequency, wherein the filter is a matched filter special for an input signal, and the frequency and the phase position of an output signal of the matched filter are the frequency and the phase position of the locked signal, so that steady state errors are not generated.

Description

technical field [0001] The present invention is a phase-locking technology widely used in the field of electronic information, and it relates to a new phase-locking theory, which adopts the sampling frequency of CAD after the frequency multiplication of the frequency-locking output signal, and then uses fast Fourier transform The method of specific output sub-filter (specific output point output signal is the phase-locked signal) method is called Selective Fast Fourier Transform or CFFT (Choose Fast Fourier Transform), specifically a lock with zero steady-state phase-locked error Phase system and phase locking method. Background technique [0002] Phase-locking technology has a history of 80 years, and has become a widely used subject. From analog to digital, from transistor to large-scale integrated circuit, it has developed rapidly, mainly to study the realization method. Their basic circuits are as figure 1 Composition: Phase Detector (PD), Loop Filter (LPF), and Voltag...

Claims

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Application Information

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IPC IPC(8): H03L7/08H03L7/099
Inventor 史田元胡蛇庆
Owner 江苏锦丰电子有限公司
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