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Memory circuit and voltage detection circuit having the memory circuit

A technology of voltage detection circuit and memory circuit, applied in static memory, read-only memory, information storage, etc., can solve the problem of increasing the scale of memory circuit circuit

Inactive Publication Date: 2014-10-29
SII SEMICONDUCTOR CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] However, in the prior art, the memory circuit requires a write circuit 105 and a read circuit 106 respectively.
Therefore, the circuit scale of the memory circuit becomes larger

Method used

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  • Memory circuit and voltage detection circuit having the memory circuit
  • Memory circuit and voltage detection circuit having the memory circuit
  • Memory circuit and voltage detection circuit having the memory circuit

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0031] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0032] First, the configuration of the memory circuit will be described. figure 1 is a diagram showing a memory circuit.

[0033] Memory circuit 1 has: "AND" circuit 2~5, "OR" circuit 6~8, inverter 9~11, "NOR" circuit 12, switch 14~17, NMOS transistor 21~23, PMOS transistor 26~ 27 . A non-volatile memory element 28 and a current source 30 .

[0034] The first input terminal of the AND circuit 2 is connected to the terminal of the signal PRX, and the second input terminal is connected to the terminal of the clock signal CLK. The switch 14 is provided between the terminal of the signal D as the first signal and the node of the signal A as the second signal, and is controlled by the output signal of the AND circuit 2 . The gate of the NMOS transistor 21 is connected to the signal P terminal, the source is connected to the ground terminal, and the drain is connected to ...

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Abstract

Provided are a memory circuit having a small circuit scale and a voltage detection circuit including the memory circuit. An NMOS transistor (21) is in an off state during loading and writing and is in an on state during reading. An NMOS transistor (22) is turned on when a high level input is received and turned off when a low level input is received. An NMOS transistor (23) is in the off state during loading and writing and is in the on state during reading. A PMOS transistor (26) is in the on state during loading and is in the off state during writing and reading. A PMOS transistor (27) is turned off when the high level input is received during loading, is turned on when the low level input is received during loading, and is in the on state during writing and reading.

Description

technical field [0001] The present invention relates to a memory circuit for reading and writing data in a nonvolatile memory element, and a voltage detection circuit including the memory circuit. Background technique [0002] In recent years, nonvolatile memory elements have been used in various electronic devices. [0003] For example, although not shown, a plurality of nonvolatile memory elements may be arranged in a matrix. Here, when data is read, the read circuit is electrically connected to the nonvolatile memory element to read data, and when the data read is completed, the read circuit is disconnected from the nonvolatile memory element. At this time, the read data is latched in the read circuit. [0004] Additionally, if Figure 10 As shown, the data of the nonvolatile memory element is appropriately read out to a circuit inside an IC (Integrated Circuit: Integrated Circuit) for use when changing the setting of the circuit. Here, the nonvolatile memory elements ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/06
CPCG11C5/143
Inventor 渡边考太郎冈智博铃木照夫
Owner SII SEMICONDUCTOR CORP