Method for producing excitation waveform during logic parameter extraction of combinational logic circuit

Abstract

The invention discloses a method for producing an excitation waveform during the logic parameter extraction of a combinational logic circuit. The technical problem to be solved is to reduce personal error during the logic parameter extraction of the combinational logic circuit. The production method comprises the following steps that: an emulational process model file and a circuit network table are input into a computer; the computer performs emulation to acquire the excitation waveform; the computer uses the excitation waveform as emulational excitation to form an emulational sequence; and the computer emulates an integrated circuit according to the emulational sequence to generate a result file of measuring information and add emulated parameter information into a format of a comprehensive library file. Compared with the prior art, the production method has the advantages that: required logic function information of a combinational logic unit is acquired by emulating the circuit network table of the combinational logic unit, so that dependence on logic function input during the generation of the excitation waveform and the emulation of the parameter extraction is avoided and the risk of the personal error among the final logic parameters generated by the circuit network table is eliminated.

Description

technical field [0001] The invention relates to an auxiliary design method of an integrated circuit, in particular to a method for generating an excitation waveform required for extracting circuit logic parameters of a combined logic unit of the integrated circuit. Background technique [0002] In today's application-specific integrated circuit ASIC design, the integrated circuit CBIC design method based on standard cell occupies a very important position. With the rapid development of ultra-large-scale integrated circuits, the design and manufacturing process of integrated circuits are updated faster and faster, and the logic parameters of standard cells, such as timing, power consumption, and setup time and hold time must also be continuously updated with the progress of the process . The extraction of standard cell logic parameters is generally done by the extractors who build a simulation environment, give appropriate excitation waveforms to each standard cell, and use ...

AI Technical Summary

Problems solved by technology

Knowing the pin name from the circuit netlist and giving the function description (function) is a relatively cumbersome and time-consuming task, and because it is still a manual operation, there is a risk of introducing human error

On the other hand, if it is a combinational logic unit or IP (Intellectual Property, Intellectual Property) module with relatively complex logic functions, its function description may need to be described by using a truth table, which is more error-prone and more cumbersome.

If the function description (function) is wrong, the parameter result of the logic unit will be wrong, it is difficult to modify, only to re-simulate

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