LDPC (low-density parity-check) decoding method

A decoding and square matrix technology, applied in the field of decoding, can solve the problems of single parallel mode and large consumption of FPGA resources, and achieve the effects of low power consumption, reduction of parallel scale, and reduction of the number of memories

Inactive Publication Date: 2011-05-25
BEIJING RES INST OF TELEMETRY +1
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Problems solved by technology

Adoption of the present invention solves the problem that in the existing partial parallel structure LDPC decoding algorithm, the parallel mode is relatively single, and the problem that the realization of the decoding algorithm needs to consume relatively large FPGA resources

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Embodiment Construction

[0019] The following provides specific implementation methods for the LDPC code with a code rate of 0.4 in the national standard DMB-TH standard. Sub-matrix A for parity check matrix H of 0.4 code rate LDPC code in the national standard DMB-TH standard i,j expressed as H q,c The form is shown in formula (1):

[0020]

[0021] where A i,j It is a matrix of 127×127, which is a cyclic matrix or a matrix of all 0s with a row weight of 1. Other relevant parameters of the H matrix are: c=35, t=59, namely the matrix H q,c It is 35 rows and 59 columns; the size of the entire H is 4445 rows and 7493 columns; the row weight is 7 and 8, and the column weight is 3, 4 and 11. The total number of 1's in the H matrix is ​​275×127.

[0022] The following sub-matrix A is represented by the position of 1 in the first row of each non-zero cyclic sub-matrix i,j , the entire parity check matrix H q,c It can be expressed in the form shown in Table 1:

[0023] Table 1 check matrix H q,c ...

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Abstract

The invention discloses an LDPC (low-density parity-check) decoding method which comprises the following steps: dividing a quasi-cyclic check matrix; grouping the divided check matrix; determining the positions of a check node and an information node in each submatrix group; determining a grouping matrix according to the positions of the check node and the information node; initializing the node information according to the structure of the grouping matrix; and decoding according to the structure of the grouping matrix. The invention solves the problems of single parallel mode and high FPGA (Field Programmable Gate Array) resource consumption for realizing the decoding algorithms in part of existing parallel structure LDPC decoding algorithms.

Description

technical field [0001] The invention relates to an LDPC decoding method, which belongs to the technical field of decoding. Background technique [0002] In recent years, LDPC codes have always been the focus of research in coding theory and industry, and a series of progress has been made. Hundreds of LDPC-related articles are published in IEEE every year. It can be seen from this that LDPC codes, as a channel coding approaching the Shannon limit, have become one of the research hotspots in the field of coding theory today, and have been written into many new communication standards, gradually entering the stage of practical application. [0003] Quasi-cyclic LDPC codes are a class of constructed codes with low-complexity coding. It can use a simple shift register to complete the encoding, and its complexity is related to the generator matrix. The optimized quasi-cyclic LDPC codes are as good as random LDPC codes in terms of bit error performance and error floor characteri...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/11
Inventor 曹雷闫慧徐松艳
Owner BEIJING RES INST OF TELEMETRY
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