System and method for automatically generating constraint file of field programmable gate array (FPGA)

A constraint file, automatic generation technology, applied in the direction of instrumentation, computing, electrical digital data processing, etc., can solve problems such as error-prone, heavy workload, complex design of FPGA constraint files, etc., to achieve the effect of ensuring accuracy and improving design efficiency

Active Publication Date: 2011-08-17
MAIPU COMM TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The technical problem to be solved by the present invention is to propose a system and method for automatically generating FPGA co

Method used

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  • System and method for automatically generating constraint file of field programmable gate array (FPGA)
  • System and method for automatically generating constraint file of field programmable gate array (FPGA)
  • System and method for automatically generating constraint file of field programmable gate array (FPGA)

Examples

Experimental program
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Embodiment

[0048] Take the generation of the FPGA constraint file on the main control board of the switch as an example,

[0049] First, check in the schematic topology data through the schematic data check-in unit:

[0050] Signal name: N1253354

[0051] Device pins connected by signal lines: R232.1, UF21.E2

[0052] (Note: R232 and UF21 are device bit numbers, and the following ".1" and ".E2" are pin numbers)

[0053] Device material number: R232(0012578)UF21(0011123)

[0054] Signal name: IN_LVTTL_ADDR13

[0055] Device pins connected by signal lines: R232.2

[0056] Then, according to the checked-in schematic topology data, enter the parsing process:

[0057] The first step is to find the FPGA device in the schematic diagram: According to the device tag naming convention, the device whose tag number starts with "R" is a resistor, and the device whose tag number starts with "UF" is an FPGA device.

[0058] In the second step, according to the searched FPGA device number, check w...

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Abstract

The invention relates to a technology for generating a constraint file in the field of logic design of a field programmable gate array (FPGA). The invention provides a method for automatically generating the constraint file of the FPGA, which aims at the problems of complicated design, large working capacity and high error probability of the constraint file of the FPGA in the prior art. Key points of the technical scheme can be summarized in that: an FPGA bit number and an effective network name which is connected with an FPGA device and meets a naming specification are analyzed according to the topological data of a schematic diagram; operation is carried out according to a pre-made rule in combination with parameter information in a parameter database of the FPGA device to determine allpin attributes of the FPGA device; and the constraint file of the FPGA is output according to a given specification of the constraint file of the FPGA at last. Furthermore, the invention also provides a system for automatically generating the constraint file of the FPGA. The invention is applied to automatic generation of the constraint file of the FPGA device.

Description

technical field [0001] The invention relates to a constraint file generation technology in the field of FPGA (programmable logic device) logic design, in particular to an automatic generation system and method for an FPGA constraint file. Background technique [0002] The FPGA constraint file is a text file with specific specifications for configuring the pin parameters of the programmable logic device. In FPGA logic design, designing FPGA constraint files is an essential link. Before the design, in order to ensure that the properties of the device pins in the schematic map correspond to the properties of the ports in the FPGA logic code, the FPGA constraint file is required to associate the device pins with the logic ports, and define the direction of the device pins, properties such as level type. [0003] In the traditional technology, the method of designing the FPGA constraint file is as follows: First, the schematic engineer searches for the FPGA device in the schema...

Claims

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Application Information

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IPC IPC(8): G06F17/50
Inventor 王隆峰
Owner MAIPU COMM TECH CO LTD
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