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Semiconductor memory device

一种存储器件、半导体的技术，应用在缺陷校正领域，能够解决存储器单元产量降低等问题

Inactive Publication Date: 2015-01-28
SEMICON ENERGY LAB CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] In recent years, the yield of memory cells tends to decrease due to the increase in the number of manufacturing steps and their complexity as the capacity of semiconductor memory devices increases

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0034] One example of a semiconductor memory device and a technique for correcting defects in the semiconductor memory device will be described in this embodiment.

[0035] First, an example of the structure of a semiconductor memory device will be referred to figure 1 be described. here, figure 1 is a circuit block diagram of the semiconductor memory device according to this embodiment. Such as figure 1 As shown, the semiconductor memory device includes a memory cell array 100 , a read driver 101 around the main memory cell array 100 , and a redundancy control circuit section 102 .

[0036] The memory cell array 100 includes a main memory unit 110, a spare memory unit, and a memory unit 114 for preventing additional writes. Note that the spare memory unit is provided with a memory unit 111 for a redundant function, a memory unit 112 for redundancy judgment, and a memory unit 113 for replacement.

[0037] The input data is written into the main memory unit 110 and the rep...

Embodiment 2

[0127] In this embodiment, an example of a method of writing data to a memory cell in a semiconductor memory device is described.

[0128] In this semiconductor memory device, when writing data to a memory cell, operation A, operation B, and operation C are alternately performed up to 4 times: operation A: write data during a predetermined period of time (for example, 75.5 μs); operation B: Data is read out during a predetermined period of time (for example, 18.9 μs); and operation C: comparing written data and read data. Note that hereinafter, data comparison by operation C is referred to as "verify function", and a series of operations A, B, and C is referred to as "verify write".

[0129] When verify writing is repeated 4 times for one memory cell, if the results of the verify function do not match each other, the resultant mismatched data α is held in the circuit as information, after which the process proceeds to the next memory cell. On the other hand, if the results of t...

Embodiment 3

[0135] In this example, refer to Figure 11 A structural example of a semiconductor device capable of wireless communication has been described. here, Figure 11 is a circuit block diagram showing a semiconductor device 900 capable of wireless communication. Such as Figure 11 As shown, the semiconductor device 900 includes a memory circuit 901 , a digital circuit 902 , an analog circuit 903 and an antenna circuit 904 .

[0136] The antenna circuit 904 receives radio waves (electromagnetic waves) emitted from the reader / writer 910 and inputs a signal obtained at this time to the analog circuit 903 . The analog circuit 903 demodulates the signal and inputs the demodulated signal to the digital circuit 902 . The memory circuit 901 performs writing and reading of data in response to an output from the digital circuit 902 .

[0137] By applying the semiconductor memory device according to the present invention to the memory circuit 901, a highly reliable semiconductor device ...

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Abstract

Easy and fast memory access with correcting defects is to be realized. In a spare memory in a semiconductor memory device, a redundant memory cell array that stores the number of correcting defects is provided. When a signal from the outside is received, the signal is switched to the redundant memory cell array, and the number of correcting defects is judged. Then, based on the result of the judgment, it is determined the judgment of a defective memory cell is continued or the judgment is finished to write data to a main memory cell. By providing the redundant memory cell array that stores the number of correcting defects, a state of correcting defects can be observed fast in such a manner.

Description

technical field [0001] The technical field relates to defect correction techniques in semiconductor memory devices. Background technique [0002] In recent years, the yield of memory cells tends to decrease due to the increase in the number of manufacturing steps and their complexity as the capacity of semiconductor memory devices increases. Therefore, in order to improve the yield of the semiconductor memory device itself, various defect correction techniques for a memory cell array including defective memory cells have been proposed. [0003] For example, a technique for correcting defects has been proposed which replaces a memory cell determined to be defective by a redundant circuit provided in a semiconductor memory device with a spare memory cell (see Patent Document 1, for example). [0004] In addition, a technique for correcting defects has been proposed, which replaces the DRAM (Dynamic Random Access Memory) in the semiconductor memory device with a redundant RAM ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C29/04
CPCG11C29/4401G11C29/808G11C16/349G11C29/44G11C2029/0409G11C2029/0411G11C16/3459G11C2029/4402
Inventor 王丸拓郎热海知昭斋藤利彦
Owner SEMICON ENERGY LAB CO LTD
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