Divider and division processing method

Abstract

The invention discloses a divider and a division processing method. The method comprises unsigned and signed division operations. An unsigned divider comprises a zero judgement unit, a zero filling unit, a shift unit, a judgement processing unit and a result processing unit. The zero judgement unit is used for judging whether a divisor is zero or not. The zero filling unit is used for filling zero to a dividend according to decimal digits to be reserved by a quotient. The shift unit is used for performing leftward movement operation of the divisor. The judgement processing unit is used for cyclically judging according to the leftward movement operation of the shift unit and the zero filled dividend output by the zero filling unit, determining each member of the quotient and inputting to the result processing unit. In the method disclosed by the invention, each member of the quotient can be obtained in turn through the approximation bit by bit by using the cycle shift of the divisor; the decimal digits to be reserved by the division result can be set according to requirements; the complex iterative operation can be avoided through the approximation bit by bit; the delay is lower; the whole operation process completely depends on shift, substraction and comparison; and the portability is strong.

Description

technical field [0001] The invention relates to a digital signal processing circuit in the technical field of communication, in particular to a divider and an operation processing method thereof. Background technique [0002] The division operation of two signed numbers is often involved in the process of modern digital signal processing, and the division operation is very difficult in the hardware implementation process. In some algorithms, through clever design, the division operation can be converted into a shift operation to achieve; But in more cases, due to the principle of the algorithm itself, it is determined that the division of two specific numbers must be completed. In the communication field, when algorithmic resource allocation is performed, it is inevitable to require FPGA to complete certain calculations that require division. [0003] In the prior art, the traditional FPGA-based division process involves multiplication operations, and the result of division...

AI Technical Summary

Problems solved by technology

However, due to the problems of interpolation accuracy and lookup table accuracy, the implementation process is more complicated

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