Method for replacing compiling chain order based on mixed-compiling order set

A technology of instruction replacement and instruction set, which is applied in the direction of program control design, instrumentation, electrical digital data processing, etc., can solve the problems of not being able to maximize the program running speed, and achieve less workload, faster link speed, and code writing easy effect

Active Publication Date: 2014-11-12
ZHEJIANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

But in this case, the processor runs these redundant instructions during runtime, and these instructions do not need to be executed, so this solution fails to maximize the running speed of the program

Method used

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  • Method for replacing compiling chain order based on mixed-compiling order set
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  • Method for replacing compiling chain order based on mixed-compiling order set

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Embodiment Construction

[0036] The present invention will be further described according to the drawings and specific embodiments below.

[0037] Here, a group of jump instructions that can realize the same function is taken as an example to illustrate the implementation method. One of the implementation cases includes three parts: instruction design, replacement rule design, and assembly link program design.

[0038] 1. Instruction design

[0039] Suppose there is a pseudo-instruction JBSR, the format is JBSR Label function is to link and jump to the subroutine, save the return address of the subroutine (the PC of the next instruction, that is, the current PC + 2) in the link register R15, and the program is transferred to the Label execute.

[0040] Corresponding to this pseudo-instruction, the processor needs to have the following machine instructions:

[0041] (1) 16-bit BSR instruction, the relevant information is as follows:

[0042] BSR16 - jump to subroutine instruction

[0043] Instructio...

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Abstract

The invention discloses a method for replacing a compiling chain order based on a mixed-compiling order set, which comprises the following steps: 1) designing more than one replacing order or a replacing order sequence with identical functions and different skip ranges and capable of enabling a processor program counter to overlook useless space according to a replaced order; 2) calculating address distance between the replaced order and a skip target, choosing a corresponding replacing order or a replacing order sequence according to a choice rule and replacing the replaced order, wherein the useless space refers to unused target document space generated after the replaced order is replaced, and the replaced order is a skip order or / and a branch order. The choice rule in step 2) is that the address distance between the replaced order and the skip target is within the skip range and time cost with order performance is the least. In an assembling process, when the address distance between the replaced order and the skip target in step 2) can not be calculated, a maximum space is reserved in the target document and relocation information A, B and C are generated for a linker. In a link process, the address distance is re-calculated, and the order is replaced according to the choice rule. The relocation information A is used for an assembler to analyze local symbols, the relocation information B is used for analyzing a target symbol by means of a constant in the link process, and the relocation information C is used for performing order replacement in the link process. The maximum space refers to the total amount of space occupied by an order or an order sequence with the largest skip range.

Description

technical field [0001] The invention relates to an optimization method for variable-length instructions in assemblers and linkers and instructions dependent on constant pools, in particular to a compilation chain instruction replacement method based on mixed instruction sets. Background technique [0002] Computer processor instructions, or machine instructions for short, are the basic inputs for the processor to work. The collection of all instructions of a processor is called the instruction set, which can be divided into: variable length (take the X86 architecture as an example), fixed length (such as only 32-bit instructions), mixed compilation (such as 32-bit instructions and 16 bit instructions exist at the same time). In addition, some instructions also depend on certain data when running (such as an indirect jump instruction requires an address constant), so when the processor is working, the instruction length required to complete the function of the instruction ca...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/45
Inventor 尹茸李莹
Owner ZHEJIANG UNIV
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