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Semiconductor device

A semiconductor and conductive technology, applied in the direction of semiconductor devices, electrical components, circuits, etc., can solve problems such as latch breakdown, and achieve the effect of low turn-on resistance and high current

Inactive Publication Date: 2012-04-18
KK TOSHIBA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, if current concentration occurs when turning off, there is a case of breakdown due to latch-up

Method used

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  • Semiconductor device
  • Semiconductor device
  • Semiconductor device

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Experimental program
Comparison scheme
Effect test

no. 1 Embodiment approach

[0046] figure 1 It is a schematic cross-sectional view of the semiconductor device of the first embodiment.

[0047] figure 2 It is a schematic diagram illustrating the planar layout of main parts of the semiconductor device. Also, in each figure, for the Figure 15 The same parts are given the same reference numerals.

[0048] The semiconductor layer includes p + type collector layer 11, n - type base layer 12, p-type base layer 13, and n + type semiconductor layer 100.

[0049] no + The type semiconductor layer 100 is called an emitter layer in the case of an IGBT, and is called a source layer in a case of a MOSFET, but the basic functions of the emitter layer and the source layer to inject electrons through the n-channel are the same. no + The n-type impurity concentration ratio of the n-type semiconductor layer 100 is n - Type base layer 12 is high.

[0050] no - type base layer 12 located at p + type collector layer 11. The p-type base layer 13 is set at n ...

no. 2 Embodiment approach

[0087] Figure 6 It is a schematic perspective view of the semiconductor device of 2nd Embodiment. exist Figure 6 In , the second main electrode 22 is indicated by a dashed-two dotted line for easy observation.

[0088] The p-type base layer 13 of this embodiment has a channel region 13a and a contact region 13b. Other configurations and obtained effects are the same as those of the above-mentioned first embodiment.

[0089] channel region 13a with n + Type semiconductor layer 100 with the same width and length overlaps in n + type semiconductor layer 100 directly below. Contact area 13b is not covered by n + Type semiconductor layer 100 is covered and pulled out upward, and is in contact with the second main electrode 22 .

[0090] Therefore, the potential of the second main electrode 22 is applied to the p-type base layer 13 , and the potential of the p-type base layer 13 can be stabilized. Accordingly, it is possible to prevent the influence of the unstable potenti...

no. 3 Embodiment approach

[0092] Figure 7 It is a schematic cross-sectional view of the semiconductor device of the third embodiment.

[0093] The semiconductor device of this embodiment has a MOSFET structure, and in figure 1 In the semiconductor device of the first embodiment shown, p + type collector layer 11 replaced by n + Type drain layer 41 structure.

[0094] On the other hand, when a desired gate potential is applied to the gate electrode 18 in a state where a high potential is applied to the first main electrode 21 and a low potential is applied to the second main electrode 22, the p-type base layer 13 and the gate An inversion layer (n-channel) is formed near the boundary surface of the electrode insulating film 17a. For example, a ground potential or a negative potential is applied to the second main electrode 22 , and a positive gate potential is applied to the gate electrode 18 . A positive potential higher than the gate potential is applied to the first main electrode 21 .

[0095...

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Abstract

According to one embodiment, a semiconductor device includes a first major electrode, a first semiconductor layer, a first conductivity type base layer, a second conductivity type base layer, a first conductivity type second semiconductor layer, a gate insulating film, a gate electrode, and a second major electrode. The gate insulating film is provided on a side wall of a trench penetrating the second conductivity type base layer to reach the first conductivity type base layer. The gate electrode is provided inside the gate insulating film in the trench. The second major electrode is provided on the second semiconductor layer and electrically connected with the second semiconductor layer. A maximum impurity concentration in the second semiconductor layer is within ten times a maximum impurity concentration in the second conductivity type base layer.

Description

[0001] This application is based on and claims the priority of Japanese Patent Application No. 2010-213221 filed on September 24, 2010, the entire contents of which are incorporated herein. technical field [0002] The present invention relates to semiconductor devices. Background technique [0003] In recent years, insulated gate bipolar transistors (Insulated Gate Bipolar Transistors, IGBTs) have been widely used as power devices with a withstand voltage of 600 V or higher. The IGBT is designed so that the current saturates and does not latch up when a current is supplied in a steady state in the forward direction. However, if current concentration occurs during shutdown, there is a possibility of breakdown due to latch-up. In particular, when the current density is increased in order to reduce the chip size and achieve miniaturization, it is required to avoid the phenomenon of breakdown (destruction) during shutdown. Contents of the invention [0004] An object of the...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/08H01L29/36H01L29/739
CPCH01L29/7397H01L29/0696H01L29/1095H01L29/4236
Inventor 小仓常雄
Owner KK TOSHIBA