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A kind of fabrication method of graphene vertical interconnection structure

A technology of vertical interconnection and fabrication method, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of poor uniformity and repeatability of carbon nanotubes, and the electrical performance is difficult to meet high-frequency and high-speed signal transmission. High conductivity, conducive to the transmission of high-frequency and high-speed electrical signals, and the effect of improving the performance of electrical signal transmission

Inactive Publication Date: 2015-07-29
PEKING UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the uniformity and repeatability of carbon nanotube growth are poor, and its electrical properties are still difficult to meet the needs of high-frequency and high-speed signal transmission.

Method used

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  • A kind of fabrication method of graphene vertical interconnection structure
  • A kind of fabrication method of graphene vertical interconnection structure
  • A kind of fabrication method of graphene vertical interconnection structure

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0034]1) First, if Figure 1a As shown, a substrate 110 is provided, and via holes 120 are formed. The substrate can be a semiconductor material, such as silicon, germanium and other simple semiconductors, or compound semiconductors such as gallium arsenide, indium phosphide, gallium nitride, etc.; it can also be a metal material, such as titanium, molybdenum, nickel, chromium, tungsten, copper, etc. Or its alloy; it can also be an insulating material such as glass or quartz. The substrate is generally circular, with notches or alignment edges made to distinguish or align crystal phases. Common substrate diameters are 50 mm, 100 mm, 200 mm, 300 mm, 450 mm, etc. Substrates can be standard thickness, ranging from 400 microns to 1000 microns, or thinned, ranging from 10 microns to 400 microns. The substrate 110 has a first substrate surface 111 and a second substrate surface 112, and the first substrate surface 111 and / or the second substrate surface 112 may have completed semic...

Embodiment 2

[0041] 1) First, if Figure 2a As shown, a substrate 110 is provided and blind vias 130 are formed. The substrate can be a semiconductor material, such as silicon, germanium and other simple semiconductors, or compound semiconductors such as gallium arsenide, indium phosphide, gallium nitride, etc.; it can also be a metal material, such as titanium, molybdenum, nickel, chromium, tungsten, copper, etc. Or its alloy; it can also be an insulating material such as glass or quartz. The substrate is generally circular, with notches or alignment edges made to distinguish or align crystal phases. Common substrate diameters are 50 mm, 100 mm, 200 mm, 300 mm, 450 mm, etc. Substrates can be standard thickness, ranging from 400 microns to 1000 microns, or thinned, ranging from 10 microns to 400 microns. The substrate 110 has a first substrate surface 111 and a second substrate surface 112, and the first substrate surface 111 and / or the second substrate surface 112 may have completed sem...

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Abstract

The invention provides a method for producing a graphene vertical interconnection structure, which comprises the following steps that: firstly, a vertical hole is produced on a substrate; then an insulation layer is produced on the surface of the substrate, and the insulation layer covers the inner surface of the vertical hole; and finally a graphene layer is produced on the insulation layer. On the basis of the graphene vertical interconnection structure, the structure can be piled in a way that from a wafer to a wafer, a chip to a wafer or a chip to a chip, and a three-dimensional integrated structure can be formed. Because of the particular ballistic distribution mechanism, the graphene has very high electric conductivity, so the transmission performance of an electric signal of the vertical interconnection structure can be improved, the transmission of a high-frequency high-speed electric signal can be facilitated, and the interference between the vertical interconnection structure and on other circuits can be reduced.

Description

Technical field [0001] The invention belongs to the technical field of manufacturing semiconductors and microsensors, and relates to a method for manufacturing a vertical interconnection structure between chips, in particular to a method for manufacturing a graphene vertical interconnection structure. Background technique [0002] The vertical interconnection between chips is a three-dimensional chip integration technology. Different from traditional packaging technology, it can provide electrical signal interconnection in the vertical direction, reduce interconnection parasitic parameters, improve system operating speed, and reduce system power consumption. The manufacturing method of the vertical interconnection structure between chips mainly includes processes such as making through holes on the chip, depositing an insulating layer in the through holes, and filling the through holes. The conductive material filling the via hole is generally metal, such as copper or tungs...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768
Inventor 陈兢朱韫晖马盛林孙新方孺牛缪旻金玉丰
Owner PEKING UNIV