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Apparatus and method for correcting at least one bit error within a coded bit sequence

A technique for encoding bit sequences, single-bit errors, applied in the field of devices with at least one single-bit error

Inactive Publication Date: 2012-05-23
INFINEON TECH AG
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] A disadvantage of prior art solutions for 1-bit and 2-bit error correction, for example, is that "all 0" and "all 1" errors are not part of the error detection

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  • Apparatus and method for correcting at least one bit error within a coded bit sequence
  • Apparatus and method for correcting at least one bit error within a coded bit sequence
  • Apparatus and method for correcting at least one bit error within a coded bit sequence

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Embodiment Construction

[0024] In the following, the same reference numerals are partly used for objects and functional units with the same or similar functional properties, and their descriptions with respect to the figures will also apply to the other figures in order to reduce redundancy in the description of the embodiments.

[0025] Before describing the proposed principles in more detail, some theoretical basis and basic terminology about linear block codes, especially Hamming codes, Shaw codes and BCH codes, are briefly introduced. These are also, for example, in "Fujiwara, E., Code Design for Dependable Systems, Wiley, 2006, p.49-53, p.98-101" and in "Tzschach, H. and Haflinger, G., Codes für den Datentransfer, Oldenburg Verlag, 1993, p.111-121".

[0026] A Hamming code is a linear block code with a code distance of 3. If m is the number of parity bits, its length is n=2 m -1. The number of data bits is k=2 m -1-m. As any linear code, a Hamming code can generally be described by a gener...

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Abstract

The present invention relates to an apparatus and a method for correcting at least one bit error within a coded bit sequence. An apparatus for correcting at least one bit error within a coded bit sequence includes an error syndrome generator and a bit error corrector. The error syndrome generator determines the error syndrome of a coded bit sequence derived by a multiplication of a check matrix with a coded bit sequence.

Description

technical field [0001] Embodiments according to the invention relate to error correction and error detection of digital signals, and in particular to an apparatus and method for correcting at least single bit errors in a coded bit sequence. Background technique [0002] Due to the high integration density of electronic circuits and memories, the frequency of errors increases. [0003] In addition to 1-bit errors, 2-bit errors and generally multi-bit errors are also increasingly taken into consideration, ie corrected and detected. In particular, in error correction, it is important to correct errors occurring quickly, if possible, in the current clock cycle in order to prevent delayed processing of corrected data compared to uncorrected data. [0004] Frequently, data is written to memory at an address and read out after a certain time. It is possible here that the data is erroneous or corrupted when it is read from the memory and needs to be corrected after it has been rea...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/05
CPCH03M13/159H03M13/155H03M13/152H03M13/616H03M13/1575H03M13/6575H03M13/151
Inventor U·巴克豪森M·格塞尔T·克恩S·拉库蒂尔T·拉比纳尔特
Owner INFINEON TECH AG
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