Cache memory system

Abstract

A cache memory is operated in a write through system, and an operation to be performed when a cache mishit occurs is performed when corresponding data is not stored in the cache memory, or only when an error occurs although there is the data. Then, a bit indicating that a soft error has occurred before is set in the cache memory, and when the bit indicates '1' and if an error has occurred again, it is determined that a hardware error has occurred, and an interrupt is generated in the CPU. The bit is to be reset at time intervals sufficiently shorter than the frequency at which it is considered that a soft error occurs.

Description

technical field [0001] The following embodiments relate to a cache memory capable of suppressing the influence of soft errors. Background technique [0002] With recent advanced semiconductor technologies, it is a general trend for semiconductor devices to have fine structures for writing and the like. However, as circuits such as writing in semiconductor devices are finer, there is a higher possibility that α rays and cosmic rays (neutron beams) received from the outside cause operational errors of circuits. For memories, small memory cells with large capacities have been produced. However, since the structure of the circuit is delicate, there is a possibility that alpha rays and cosmic rays (neutron beams) cause errors in the stored data. This error is called a soft error. Soft errors can be caused in both main memory and cache memory. [0003] A write system for the cache memory may be a write-back system and a write-through system. It is known that although the writ...

AI Technical Summary

Problems solved by technology

It is known that although the write-back system has higher computing speed and performance, the control of the write-back system is more complicated

However, for soft errors, write-through systems are recommended for soft errors, because in write-ba

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