Semiconductor device structure and method for manufacturing same

Abstract

A method for manufacturing a semiconductor device structure includes: providing a front-end device structure which comprises a semiconductor substrate; etching the semiconductor substrate to form grooves in portions, about to form a source / drain region, of the semiconductor substrate, so that a dummy gate structure is formed on a portion between the grooves; forming transverse diffusion barrier walls on the semiconductor substrate, wherein the transverse diffusion barrier walls are positioned on two sides of the dummy gate structure and close to the dummy gate structure; and forming a substrate epitaxial layer on the surface of the semiconductor substrate and the surface of the dummy gate structure, and planarizing the substrate epitaxial layer. The method is capable of effectively suppressing transverse diffusion of impurities in the source / drain region and enables the transverse diffusion to be designed separately from longitudinal diffusion, so that SCE (short channel effect) and overrun of the S / D (source / drain) region of a semiconductor device can be improved, and further integral electric property of the semiconductor device is improved.

Description

technical field [0001] The present invention relates to a semiconductor manufacturing process, and in particular, to a semiconductor device structure and a manufacturing method thereof. Background technique [0002] For a long time, in the semiconductor manufacturing process, the size reduction of gate and channel has been limited by the development of source / drain (S / D) junction and gate dielectric. Although the lightly doped source-drain (LDD) process and high dielectric constant (high-k) materials have been adopted, the short-channel effect (hereinafter referred to as the SCE effect) still faces major challenges. The SCE effect leads to various secondary effects in transistors, such as carrier velocity saturation effect that affects carrier mobility, hot carrier effect (HCE) that shortens device lifetime, and leakage induced degradation that deteriorates subthreshold characteristics. Barrier lowering effect (DIBL), which leads to increased leakage current between source ...

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Problems solved by technology

[0004] It is not difficult to understand from the above description that although the ultra-shallow abrupt junction process can improve the SCE effect, if the lateral and vertical diffusion of impurities cannot be effectively controlled, the electrical characteristics of the semiconductor device may be deteriorated. For the two-step S / D This is especially true for injected NMOS transistors

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