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Method and device for realizing hardware fault detection on PCIE (peripheral component interconnect express)

A hardware failure and implementation method technology, applied in the field of PCIE hardware failure detection, can solve problems such as difficult integration, low detection efficiency, inconvenient large-scale production of products, etc., and achieve the effect of reducing complexity and improving efficiency

Active Publication Date: 2012-09-12
BEIJING XINWANG RUIJIE NETWORK TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] Although the PCIE standard has been more and more widely used, in terms of PCIE fault detection, the existing detection scheme is relatively complicated. Although there are special test cards or test platforms to detect faults, it is not easy to integrate and inconvenient for product installation. mass production
Moreover, the existing detection scheme is completed by pure hardware detection, which lacks the intelligence and automation of detection, and the detection efficiency is low.

Method used

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  • Method and device for realizing hardware fault detection on PCIE (peripheral component interconnect express)
  • Method and device for realizing hardware fault detection on PCIE (peripheral component interconnect express)
  • Method and device for realizing hardware fault detection on PCIE (peripheral component interconnect express)

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Embodiment 1

[0023] Embodiment 1 of the present invention provides a kind of implementation method of PCIE hardware failure detection, and the step flow of this method is as follows figure 1 shown, including:

[0024] Step 101. Determine the state value of the first link negotiation mode.

[0025] In this step, the first link negotiation mode state value corresponding to the terminal equipment EP may be determined. Specifically, the data in the loop status Link-Status register in the status register (RC, EP, Switch hardware status register) of the PCIE can be read through the root component RC, and the real-time data truly reflects the current link The negotiation status of the link, and the first link negotiation mode status value can be determined according to the data.

[0026] Step 102: Compare the state value of the first link negotiation mode with the state value of the second link negotiation mode.

[0027] In this step, the determined first link negotiation mode status value may...

Embodiment 2

[0036] Embodiment 2 of the present invention provides a kind of implementation method of PCIE hardware fault detection, and the step flow of this method is as follows figure 2 shown, including:

[0037] Step 201, initialization.

[0038] In the initialization process, the Link negotiation mode status value configured in PCIE (the second link negotiation mode status value) can be read and pre-stored in the flash. As a reference value, the value may be 1, 4, 8, 16, etc. kind of value.

[0039]Step 202, start PCIE hardware fault detection.

[0040] Step 203, perform a read and write test.

[0041] In this step, the RC root component can be used to read and write the set address in the PCIE mapping address space of the EP device to be detected, first write a fixed value, and then read the value in the set address, Comparing the written value and the read value, if the written value is not equal to the read value, it is determined that there is a hardware failure in the PCIE, ...

Embodiment 3

[0054] Embodiment 3 of the present invention provides a kind of implementation device of PCIE hardware failure detection, the structure of this device can be as follows image 3 shown, including:

[0055] The first state value determination module 11 is used to determine the first link negotiation mode state value corresponding to the terminal equipment EP; the comparison module 12 is used to compare the determined first link negotiation mode state value with its pre-stored second link The negotiation mode state value is compared, and the second link negotiation mode state value represents the link negotiation mode state value corresponding to the PCIE under normal working conditions; the fault determination module 13 is used to determine that a hardware fault occurs in the PCIE when the comparison result is inconsistent.

[0056] The first status value determination module 11 is specifically configured to read the data in the loop status Link-Status register in the status reg...

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Abstract

The embodiment of the invention provides a method and a device for realizing hardware fault detection on a PCIE (peripheral component interconnect express). The method comprises the following steps: comparing a first negotiation model state value which corresponds to terminal equipment (EP) with a prestored second negotiation model state value, wherein a second link negotiation model state value represents a link negotiation model state value corresponding to the PCIE under a normal work state; and determining the occurrence of the hardware fault on the PCIE when determining that the first negotiation model state value is not equal to the second negotiation model state value. The complexity of the hardware fault detection on the PCIE is lowered and simultaneously the efficiency of the hardware fault detection on the PCIE is improved.

Description

technical field [0001] The present invention relates to the communication field, in particular to a method and device for realizing PCIE hardware fault detection. Background technique [0002] Peripheral Component Interconnect Express (PCIE, Peripheral Component Interconnect Express) has the advantage of high data transmission rate. At present, PCIE has several specifications such as x1, x4, x8, x16, etc., among which, x1 means that there is 1 pair of read and write loops, and x4 means that there are 4 For the read-write loop, x8 means that there are 8 pairs of read-write loops, and x16 means that there are 16 pairs of read-write loops, and there are versions 1.0 and 2.0. The 16X 2.0 version with the highest data transmission rate can reach 10GB / s, and there is still considerable development potential. From PCIE 1X to PCIE16X, it can meet the needs of low-speed devices and high-speed devices that will appear in a certain period of time now and in the future. Now mainstream...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/22
Inventor 周勇
Owner BEIJING XINWANG RUIJIE NETWORK TECH CO LTD