Digital DLL for timing control in semiconductor memory

Abstract

A semiconductor memory includes a delay locked loop (DLL) configured to generate a timing code based on a clock signal. A plurality of memory devices are coupled to the DLL. Each of the plurality of memory devices is configured to generate internal control signals for operating a memory array based on the timing code received from the DLL.

Description

technical field [0001] The disclosed systems and methods relate to semiconductor memory. More specifically, the disclosed systems and methods relate to timing control of multiple embedded dynamic random access memory (eDRAM) modules. Background technique [0002] The reduction in technology scale allows a large number of system components to be located on a single chip. From below 65nm, computing chips and networking chips include multiple cores, which require each chip to have a large amount of memory. Given the need for high-speed random access, static random access memory ("SRAM") is often the first choice. However, as on-chip memory density increases, the increased leakage energy per transistor makes SRAM less attractive. At the same time, process fluctuations also affect the stability of the SRAM cell and reduce the static noise margin (especially at low voltages). In high-power-sensitive designs with embedded memory, system designers turn to embedded DRAM, which co...

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Problems solved by technology

However, as on-chip memory density increases, the increased leakage energy per transistor makes SRAM less attractive

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