Data transmission method and data interface card

Abstract

The application discloses a data interface card which comprises a field programmable gate array (FPGA), a special integrated circuit, a first random storage module and a second random storage module, wherein the FPGA is used for receiving data of a first format from an upper interface, carrying out deserialization and de-encapsulation on the data of the first format, extracting effective data and the port number of a lower interface, and generating storage state information corresponding to effect data; the effect data is stored to the first random storage module; the storage state information corresponding to the effective data and the port number of the lower interface are stored into the second random storage module; corresponding effective data is read from the first random storage module according to the storage state information of the effective data read from the second random storage module, and the effective data is recovered into a data pocket; and the data pocket is transmitted to the special integrated circuit according to the port number of the lower interface read from the second random storage module. The application also discloses a data transmission method.

Description

technical field [0001] The present application relates to the technical field of data storage, in particular to a data transmission method and a data interface card. Background technique [0002] In the practical application in the field of data storage technology, the type of the uplink interface is different from that of the downlink interface. The biggest difference between the uplink interface and the downlink interface mainly lies in the difference in data format and rate. In order to realize the data transmission between different interfaces, the Field Programmable Gate Array (FPGA, Field Programmable Gate Array) is generally used to realize the data format conversion, and the random access memory (RAM, Random Access Memory) outside the FPGA is used as a buffer. Matching at different rates. [0003] The following is an example of how the uplink interface is a 10 Gigabit Ethernet interface and the downlink interface is a packet technology (POS, Pakage Over Synchronous ...

AI Technical Summary

Problems solved by technology

[0031] 3. The FPGA code implementation is relatively complicated, because the FPGA needs to maintain the buffer descriptor table when storing data, and when reading data, it is necessary to obtain the pointer of the data buffer first, and then extract the data according to the total data length

[0032] Due to the above shortcomings, the storage capacity and access speed of RAM will be reduced, which will affect the maximum data bandwidth of the downlink port.

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