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Reducing susceptibility to electrostatic discharge damage during die-to-die bonding for 3-D packaged integrated circuits

A technology of integrated circuits and bare chips, which is applied in the direction of circuits, electrical components, and electrical solid-state devices, and can solve problems such as packaging of integrated circuits with single bare chips

Inactive Publication Date: 2014-11-05
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Also, current methods of reducing the likelihood of an ESD event, such as grounding the die or ionizing the surrounding air, may not be as effective in TSS packaging technology as in single die integrated circuit packaging

Method used

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  • Reducing susceptibility to electrostatic discharge damage during die-to-die bonding for 3-D packaged integrated circuits
  • Reducing susceptibility to electrostatic discharge damage during die-to-die bonding for 3-D packaged integrated circuits
  • Reducing susceptibility to electrostatic discharge damage during die-to-die bonding for 3-D packaged integrated circuits

Examples

Experimental program
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Effect test

Embodiment Construction

[0016] In the description that follows, the scope of the term "some embodiments" is not limited to mean more than one embodiment, but the scope may include one embodiment, more than one embodiment, or possibly all embodiments.

[0017] figure 1 is a cross-sectional view (not drawn to scale) of the second tier die and the first tier die before attachment and bonding. figure 1 A first tier die 102 is illustrated in , having a set of conductive bumps 104 attached to a package substrate 106 . For ease of illustration, the under bump metallization layer for the conductive bump 104 is not shown. The second tier die 108 will be attached to the set of conductive bumps 110 on the first tier die 102 . Conductive bumps 110 may be formed on the backside of the first tier die 102 . Die attach is performed at a temperature that may cause warping of package substrate 106 and die 102 . This warping may be at figure 1 in exaggeration.

[0018] figure 1 A set of conductive bumps on the b...

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PUM

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Abstract

Mitigating electrostatic discharge damage when fabricating a 3-D integrated circuit package, wherein in one embodiment when a second tier die is placed in contact with a first tier die, conductive bumps near the perimeter of the second tier die that are electrically coupled to the substrate of the second tier die make contact with corresponding conductive bumps on the first tier die that are electrically coupled to the substrate of first tier die before other signal conductive bumps and power conductive bumps on the second tier and first tier dice make electrical contact.

Description

technical field [0001] The present invention relates to the manufacture of electronic integrated circuit packaging, and more particularly to mitigating electrostatic discharge damage during the manufacture of 3D packaged integrated circuits. Background technique [0002] In some integrated circuit stacked die packages, such as 3D or TSS (Through Silicon Stacking) integrated circuit packages, two or more dies (chips) are stacked on top of each other. For example, a first tier die can be bonded to a packaging substrate, and a second tier die can be bonded on top of the first tier die. The conductive bumps on the bottom of the second tier die are electrically coupled to the conductive bumps on the top of the first tier die. This electrical coupling can be achieved by soldering. The first tier die and the second tier die may be positioned relative to each other such that their active sides face each other. As another example, the active side of the second tier die may be loca...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/98H01L25/065H01L21/60
CPCH01L2224/81801H01L24/17H01L25/0657H01L24/14H01L2224/14177H01L2225/06527H01L2224/16225H01L2924/3511H01L2224/1403H01L23/49833H01L2224/14136H01L2224/17517H01L2224/14179H01L2924/15311H01L2224/14135H01L2924/01057H01L2225/06517H01L2224/81194H01L25/50H01L2224/14133H01L2924/014H01L2224/16145H01L2225/06513H01L2224/81986H01L2924/01033H01L24/81H01L23/50H01L2924/14H01L2924/00H01L25/065H01L23/60
Inventor 布雷恩·马修·亨德森阿尔温德·钱德拉舍卡朗
Owner QUALCOMM INC