A method of returning fetched data in cache in advance

Abstract

The invention provides a method for returning access data in advance in a cache. The method comprises the following processes of: (1) sending an access request by a core; (2) if finding out that the cache is not accurate by traversing a cache assembly line for a first time, sending a read request to a next-level cache or access controller; (3) executing read operation by using the next-level cache or access controller, so as to return the data to the cache; (4) returning the data to the core; and (5) filling the data responding a returning order to the cache. With the adoption of the method provided by the invention, the access speed can be greatly improved, and the hardware cost is reduced.

Description

technical field [0001] The invention mainly relates to the field of cache pipeline design in multi-core microprocessors, in particular to a method for returning accessing data in cache in advance. Background technique [0002] In modern microprocessor design, its storage system often uses cache to reduce memory access delay. The memory access instructions processed by the cache mainly include load and store instructions, and the execution of the processor is more sensitive to the delay of the load instruction. If the load hits in the cache, the data will be returned quickly, and if it does not hit, there will be a longer delay. In the design of high-efficiency microprocessors, in order to return the memory access instruction on the mission earlier, a shorter pipeline is often used. The instruction that does not hit needs to pass through the pipeline multiple times to complete, and multiple executions will lead to the execution time of the memory access instruction that does...

AI Technical Summary

Problems solved by technology

In the cache with a short pipeline, the memory access request that does not hit has to go through the pipeline at least three times, resulting in a large delay in the memory access that does not hit the cache.

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