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Manufacturing method of package substrate

A manufacturing method and technology for packaging substrates, which are used in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., and can solve problems such as foreign matter

Active Publication Date: 2015-08-19
ASE SHANGHAI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] In view of this, the present invention provides a packaging substrate and its manufacturing method to solve the problem of foreign matter such as chips and burrs generated by mechanical drilling of the current substrate.

Method used

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  • Manufacturing method of package substrate
  • Manufacturing method of package substrate
  • Manufacturing method of package substrate

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Embodiment Construction

[0015] The following descriptions of the various embodiments refer to the accompanying drawings to illustrate specific embodiments in which the present invention can be practiced. Furthermore, the directional terms mentioned in the present invention are, for example, up, down, top, bottom, front, back, left, right, inside, outside, side, surrounding, central, horizontal, transverse, vertical, longitudinal, axial, The radial direction, the uppermost layer or the lowermost layer, etc. are only directions referring to the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present invention, but not to limit the present invention.

[0016] Please refer to Figure 1A , 1B As shown, the packaging substrate 1 of an embodiment of the present invention mainly includes a first insulating layer 11, an inner circuit layer 12, a second insulating layer 13, a first outer circuit layer 14, a first solder resist layer 15, A second outer circu...

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Abstract

The invention discloses a package substrate and a manufacturing method thereof. The package substrate comprises a first insulated layer, an internal circuit layer and second insulating layers, wherein the internal circuit layer is formed on the inner surface of the first insulating layer; the first insulating layer and the internal circuit layer are covered with the second insulating layers; the first insulating layer is provided with an etching concave part which exposes an adjacent surface of each second insulating layer; and a smooth inner wall surface is arranged on the etching concave part. The inner wall surface of the etching concave part is smoothened by adopting a mode of electroplating metal and removing the metal by etching, so that scraps or burrs generated by mechanical drilling can be eliminated; and compared with a mechanical drilling mode, the arrangement mode and the shape of the etching concave part have better design flexibility.

Description

technical field [0001] The present invention relates to a packaging substrate and a manufacturing method thereof, in particular to a packaging substrate capable of embedding chips and a manufacturing method thereof. Background technique [0002] Existing semiconductor packaging substrates, such as board-on-chip (BOC) packaging substrates, are manufactured in the following way: use a milling cutter to mechanically drill holes on a substrate to form through holes, and place holes in specific areas of the substrate. Form a dry film, and then perform operations such as exposure, development, and etching to facilitate the formation of surface circuits on the substrate, so that a chip-on-board packaging substrate can be obtained. During packaging, the chip can be placed on the upper surface of the packaging substrate, and then the bonding wire is electrically connected to the pad formed by the circuit on the lower surface of the substrate through the through hole, and then the thr...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/498H01L21/48
CPCH01L2224/48091H01L2224/48227
Inventor 罗光淋王德峻方仁广
Owner ASE SHANGHAI