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Semiconductor integrated circuit device

An integrated circuit and semiconductor technology, applied in the field of semiconductor integrated circuit devices, can solve the problems of shortening the data transmission period, difficult timing tolerance, etc., and achieve the effect of improving characteristics

Active Publication Date: 2018-03-06
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As data transfer speeds increase, data transfer periods become shorter, making it increasingly difficult to secure timing margins

Method used

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  • Semiconductor integrated circuit device
  • Semiconductor integrated circuit device
  • Semiconductor integrated circuit device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach 1

[0101] figure 1 Shown is a block diagram showing an example of the configuration of the semiconductor integrated circuit device 1 and the semiconductor integrated circuit device 2 in Embodiment 1 of the present invention. figure 2 shown is figure 1 An explanatory diagram of the connection portion of the semiconductor integrated circuit device 1 and the semiconductor integrated circuit device 2 in . Figure 3A with Figure 3B shown is figure 2 An explanatory diagram of an example of the structure of the I / O module. Figure 4 Shown is an explanatory diagram of an example of an input buffer used as an I / O module at the time of study of the present invention. Figure 5A to Figure 5C shown is Figure 4 An explanatory diagram of an example of DC characteristics in a differential amplifier circuit. Image 6 shown is Figure 4 An explanatory diagram of an example of an input waveform and an output waveform in a differential amplifier circuit. Figure 7 shown is Figure 3A w...

Embodiment approach 2

[0194] Figure 11 It is an explanatory diagram showing an example of the configuration of an I / O module that inputs a differential signal in Embodiment 2 of the present invention.

[0195]

[0196] The outline of Embodiment 2 of the present invention will be described below. Embodiment 2 has described a semiconductor integrated circuit device having an I / O circuit (I / O module 89) having a first terminal for inputting one end of a differential signal. The input buffer (input buffer 30), the second input buffer (input buffer 31) that inputs the other end of the differential signal, the first output buffer (output buffer 32) that inputs one end of the differential signal, and the input differential signal The second output buffer (output buffer 33) at the other end. Wherein, the first input buffer has a first differential amplifier circuit that amplifies the first signal (clock signal DQS) in the differential signal and outputs it, and the second input buffer has a circuit th...

Embodiment approach 3

[0209] Figure 12 Shown is an explanatory diagram of an example of the configuration of an I / O module to which a clock signal is input in Embodiment 3 of the present invention, Figure 13 shown is Figure 12 An explanatory diagram of an operation example of the delay adjustment circuit set in the I / O module.

[0210] In Embodiment 3, the I / O module 89 is the same as Embodiment 2 Figure 11 The same configuration is a configuration in which a delay adjustment circuit 34 is added. The delay adjustment circuit 34 is composed of inverters 35 to 40 .

[0211] The inverters 35 to 37 and the inverters 38 to 40 are connected in series, respectively. The input of the inverter 35 is connected to the output of the input buffer 30 , and the input of the inverter 38 is connected to the output of the input buffer 31 . A signal ZB is output from an output unit of the inverter 37 , and a signal Z is output from an output unit of the inverter 40 . The delay adjustment circuit 34 is a cir...

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PUM

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Abstract

The invention discloses a method for improving the output signal characteristics of a differential amplifier circuit. When the input data signal is at "Low" level, the current I1 flowing through the transistor 16 decreases, and the potential at the connection portion (node ​​D) between the resistor 14 and the resistor 14a becomes high. The potential is input (negative feedback) to the gate of the transistor 18 to increase the potential of the gate, thereby adjusting the amount of tail current I_TAIL. When the input data signal is at "High" level, the potential of the node D drops due to the excessive current I1. Therefore, the gate potential of the transistor 18 will drop (negative feedback), and the tail current I_TAIL can be adjusted. Therefore, the difference in delay time from the output waveform can be shortened by the rising and falling edges of the input waveform.

Description

technical field [0001] The present invention relates to a semiconductor integrated circuit device, and more particularly to an effective technique for connecting an interface circuit of other semiconductor integrated circuit devices. Background technique [0002] When connecting a semiconductor integrated circuit device such as SDRAM (Synchronous Dynamic Random Access Memory) to a semiconductor integrated circuit device such as a microcomputer, an interface circuit must be provided in each device. The interface circuit is designed according to the international standard specifications of various SDRAMs. [0003] The standard specifications of SDRAM include DDR (Double Data Rate: Double Data Rate) specification, DDR2 specification, DDR3 specification, LPDDR (Low Power Double Data Rate: Low Power Double Data Rate) specification, and LPDDR2 specification. [0004] The DDR specification has a DDR function that can simultaneously read and write data when the clock signal rises a...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C7/10G11C11/4096G11C7/06
CPCG11C7/10G11C7/1057G11C7/1072G11C7/1084G11C11/4093G11C11/4096G11C11/4076G11C11/4091G11C11/409G11C7/06
Inventor 池端菜月田中一雄户羽健夫荒川政司
Owner RENESAS ELECTRONICS CORP