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Method and device for realizing variable width link

A link and width technology, applied in data exchange through path configuration, climate sustainability, digital transmission system, etc., can solve problems such as increasing delay

Inactive Publication Date: 2016-08-17
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This increased latency may not be acceptable for such systems

Method used

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  • Method and device for realizing variable width link
  • Method and device for realizing variable width link
  • Method and device for realizing variable width link

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Embodiment Construction

[0023] In the following description, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In addition, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the understanding of this description.

[0024] Throughout this specification, "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout the specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments.

[0025] Furthermore, inventive aspects lie in some features of a single disclosed embodime...

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Abstract

Embodiments of the invention provide an algorithm for dividing a link into one or more reduced-width links. For one embodiment of the invention, a multiplexing scheme is employed to effect a bit transmission order required by a particular cyclic redundancy check. The multiplexed output bits are then swizzled on-chip to reduce on-board routing congestion.

Description

[0001] This application is a divisional application of the patent application with the filing date of December 3, 2004, entitled "Method and Device for Realizing Variable Width Links", and application number 200410096571.6. technical field [0002] Embodiments of the present invention relate generally to the field of processing systems using link-based interconnection schemes, and more particularly, to methods and apparatus for logically decomposing a single link interface into quadrants to support Variable link width, lane reversal and port bifurcation features. Background technique [0003] To address the shortcomings of bus-based interconnection schemes for multiprocessor systems (MPS), point-to-point link-based interconnection schemes have been developed. Each node of such a system includes agents (eg, processors, memory controllers, I / O hub components, chipsets, etc.) and routers for transferring data between the connected nodes. Agents of such a system transfer data b...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/40G06F13/38H04L12/26H04L12/28H04L29/08
CPCG06F13/4009G06F13/4018Y02D10/00
Inventor 莫里斯·B·斯坦曼拉胡尔·R·沙阿纳韦恩·谢吕库里阿龙·T·斯平克艾伦·J·鲍姆桑贾伊·达布罗提姆·弗罗德沙姆戴维·S·邓宁西奥多·Z·舍恩博恩
Owner INTEL CORP