Sampling device and sampling method for source-synchronous double data rate (DDR) interface

Abstract

The invention relates to a sampling device and a sampling method for a source-synchronous DDR interface. The device comprises a delay module, a de-serialization module, a parallel processing module and a clock domain switching module. The delay module is used for delaying input clock signals and outputting the clock signals meeting timing sequence requirements; the de-serialization module is used for deserializing input data signals or control signals according to the clock signals output by the delay module; and the parallel processing module is used for recognizing effective data in the data signals according to the control signals output by the de-serialization module and converting output timing sequences of the valid data into write interface timing sequences of the clock domain switching module; and the clock domain switching module is used for caching the valid data according to the write interface timing sequences and outputting the valid data according to the received write interface timing sequences. According to the sampling device and the sampling method, a phase-locked loop module is not utilized, limited logical resources are prevented from being occupied, and restrictions by the number of internal logical clock resources of field programmable gate array (FPGA) devices are reduced.

Description

technical field [0001] The invention relates to the technical fields of communication and electronics, in particular to a sampling device for a source synchronous double data rate DDR interface and a sampling method thereof. Background technique [0002] With the improvement of the processing performance of the chip, the rate of the external physical interface of the chip is also increased accordingly. In order to reduce the interconnection lines between the chips on the single board, the interface with clock double-edge sampling is usually used. [0003] DDR (Double Data Rate, double data rate) technology, that is, data is transmitted on both the rising edge and the falling edge of the clock, which can double the data transmission rate while keeping the clock rate constant. Therefore, the DDR interface is widely used For the interconnection between chips, for example: RGMII interface (Reduced Media Independent Interface, simplified media independent interface), XGMII (10 Gi...

AI Technical Summary

Problems solved by technology

[0006] Because the logic needs to occupy a phase-locked loop and global (or local) clock routing resources when performing data sampling processing for each group of physical interfaces of this type, multiple interfaces need to occupy multiple PLL or DLL modules. However, for FPGA Generally speaking, PLL / DLL and global / local clock resources are limited (for example: the largest chip of altera S4 GX series, EP4SGX530, has only 12 PLL resources), which need to be optimized and used, which cannot meet the situation of a large number

Moreover, the clock phases delayed by 90 degrees and 270 degrees output by the phase-locked loop module 100 are only theoretical values. Due to the uncertainty of the layout delay of the clock line, this phase is not necessarily the most suitable sampling phase point, which cannot be determined according to The actual layout is adjusted

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