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Address decoding method and semiconductor memory device using the same

A memory device and address decoding technology, which is applied in the field of semiconductor memory devices, can solve the problems of overlapping enabling periods, errors in reading and writing operations of semiconductor memory devices, etc.

Active Publication Date: 2013-05-08
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, since the input of the strobe clock signal CSTR is delayed, the input timing of the internal addresses IADD1 and IADD2 generated according to the second combination of addresses ADD is the same as the strobe The enabling period of the clock signal CSTR overlaps
In this case, the output enable signal Yi which is enabled according to the first combination of addresses ADD And the output enable signal Yi which is enabled according to the second combination of addresses ADD is enabled, so errors may be generated in the read and write operations of the semiconductor memory device

Method used

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  • Address decoding method and semiconductor memory device using the same
  • Address decoding method and semiconductor memory device using the same
  • Address decoding method and semiconductor memory device using the same

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Embodiment Construction

[0021] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, the examples are for illustrative purposes only and are not intended to limit the scope of the present invention.

[0022] figure 2 is a block diagram illustrating the configuration of a semiconductor memory device according to one embodiment of the present invention.

[0023] see figure 2 , the semiconductor memory device includes a gate clock generator 10 , an internal address generator 20 and an output enable signal generator 30 . The gate clock generator 10 is configured to generate a gate clock signal CSTRN having a plurality of test mode signals selectively enabled according to a plurality of test mode signals such as the first The controlled delay amount for one to the third test mode signal TM. The internal address generator 20 is configured to latch addresses ADD in response to a first level of the strobe clock signal CSTRN, an...

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Abstract

A semiconductor memory device includes: a strobe clock generator configured to generate a strobe clock signal having a delay time controlled according to a plurality of test mode signals which are selectively enabled in response to a read signal or write signal; an internal address generator configured to latch an address in response to a first level of the strobe clock signal, and generate an internal address by decoding the address in response to a second level of the strobe clock signal; and an output enable signal generator configured to decode the internal address and generate output enable signals which are selectively enabled.

Description

[0001] Cross References to Related Applications [0002] This application claims priority from Korean Patent Application No. 10-2011-0116135 filed with the Korean Intellectual Property Office on Nov. 8, 2011, the entire contents of which are hereby incorporated by reference. Background technique [0003] A semiconductor memory device stores data or outputs stored data according to an operation mode. For example, when an external device such as a central processing unit (CPU) requests data, the semiconductor memory device performs a read operation or performs a write operation whose output corresponds to an address input by the above-mentioned external device requesting data. data, the write operation is to store the data provided by the external device to the location corresponding to the above address. [0004] The address path is utilized to perform read and write operations. The address path includes a row address path where the sense amplifier senses and amplifies the da...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C8/04
CPCG11C8/04G11C29/1201G11C29/18G11C8/18G11C29/12015G11C8/10
Inventor 秋新镐
Owner SK HYNIX INC