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Chip size packaging structure and chip size packaging method thereof

A chip size packaging and chip technology, which is applied in semiconductor/solid-state device components, semiconductor devices, electrical components, etc., can solve the problem of high difficulty in coupling chips and external circuits

Active Publication Date: 2016-02-10
KING YUAN ELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] In view of this, how to improve the difficulty of coupling between the chip and external circuits in traditional chip-scale packaging is an urgent goal for the industry.

Method used

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  • Chip size packaging structure and chip size packaging method thereof
  • Chip size packaging structure and chip size packaging method thereof
  • Chip size packaging structure and chip size packaging method thereof

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Experimental program
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Embodiment approach

[0039] Further, the chip substrate 3a including the redistribution circuit means that during the manufacturing process of the chip substrate 3a, the connection circuits in the substrate 3 have been rearranged according to different requirements, so as to adjust the coupling of the connection pads 111 of the polished wafer 1 to the The corresponding connection point positions of these external connection pads 331 of the chip substrate 3a. Therefore, compared with the chip substrate 3a that does not contain redistribution lines, which can only implement point-to-point direct coupling, the chip substrate 3a that contains redistribution lines can be coupled to at least one of these external connection pads 331 because of its redistribution lines, making the chip The external connection pads 331 of the substrate 3 a and the connection pads 111 of the polished wafer 1 can be more elastically and flexibly coupled by redistribution lines.

[0040] Image 6 It is a schematic diagram o...

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Abstract

The invention provides a chip size packaging structure and a chip size packaging method thereof. The chip size packaging method comprises the following steps: grinding a bottom surface of a wafer; arranging a bottom surface of a substrate on a carrier; bonding the ground bottom surface of the wafer to a top surface of the substrate through an adhesive layer; separating the carrier; coupling connection pads of the wafer to external connection pads of the substrate, wherein the connection pads are formed on a top surface of the wafer and the external connection pads are formed on a bottom surface of the substrate ; and cutting the wafer into a plurality of chip size package structures.

Description

technical field [0001] The present invention relates to a chip size packaging structure and a chip size packaging method thereof; more specifically, the present invention relates to a chip size packaging structure and a chip size packaging method coupled with an external circuit through a back-end output. Background technique [0002] For the semiconductor industry, packaging and testing are classified as back-end processes, in which packaging operations are mainly used to provide product protection, heat dissipation, and conduction circuits. The traditional packaging operation is to use plastic, ceramic, or metal materials to package the chip (chip) cut from the wafer (Wafer) to protect the chip from external pollution and realize the electrical connection between the chip and the electronic system. Sexual connection, physical support and heat dissipation. [0003] With the advancement of technology, chips are also developing in a diversified direction, and under the marke...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/60H01L21/50H01L23/488H01L23/528
CPCH01L2224/32145H01L2224/48091H01L2224/73265H01L2924/00014
Inventor 林殿方
Owner KING YUAN ELECTRONICS