Split gate flash memory unit and manufacturing method thereof

Abstract

The invention provides a split gate flash memory unit and a manufacturing method thereof. When a superfluous accumulated oxide layer on a semiconductor substrate is etched before word-line oxide is formed, the accumulated oxide layer is firstly etched in a dry mode and then is etched in a wet mode, after the accumulated oxide layer on the semiconductor substrate is etched and removed, the bottom end, close to the semiconductor substrate, of the etched residual oxide layer on the outer surface of the oxide layer on the side wall can have a smooth feature through the utilization of the characters of anisotropy of dry etching and anisotropy of wet etching, then the thickness of the word-line oxide layer on the side where a floating gate is located is increased, BTBT occurrence probability in the area is reduced, the emergence of free electrons in the area is restrained, and the programming interference relative to the mechanism is reduced.

Description

technical field [0001] The invention relates to the field of semiconductor technology, in particular to a split gate flash memory unit and a manufacturing method thereof. Background technique [0002] A typical example of a nonvolatile memory device with electrical programming and erasing functions is a flash memory (Flash memory). The memory cells of the flash memory can be classified into a stack structure and a split gate structure. Stacked flash memory cells are prone to repeated write / erase cycles, and the cell threshold may be changed, that is, the problem of excessive erase function, and the separation gate can overcome this problem well. A typical separation Gate memory cells such as figure 1 As shown, it includes a semiconductor substrate 100 having a source 111, a floating gate oxide layer 101, a floating gate 102, an inter-gate dielectric layer 103, a control gate 104, and a control gate silicon nitride layer formed sequentially on the semiconductor substrate 10...

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Problems solved by technology

However, due to the shrinking size of memory devices, such as figure 1 In the split-gate memory cell shown, the word line oxide layer 113 is getting thinner and thinner. Based on the generation principle similar to MOSFET gate-to-drain leakage (GIDL) current, the word line oxide layer between the word line 122 and the floating gate 102 A band-band tunneling (BTBT) effect will occur on the semiconductor substrate corresponding to the bottom portion A of the layer 113 near the bottom portion A of the semiconductor substrate 100 (that is, the corner formed by the word line oxide layer 113 and the floating gate sidewall oxide layer 109), and then Free electrons are generated by band-band tunneling, and these free electrons tunnel through the oxide layer there and inject into the floating gate 102 under the action of the high voltage of the control gate, thus changing the state of the floating gate and causing program disturbance. Seriously affect memory endurance and data retention

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