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semiconductor integrated circuit

A technology of integrated circuits and semiconductors, which is applied in the field of semiconductor integrated circuits and can solve problems such as difficulties in circuit integration and mutual interference of circuits.

Inactive Publication Date: 2015-11-25
SHARP KK
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] As mentioned above, since the LNB handles relatively high frequencies, mutual interference between circuits is prone to occur
So in the past, the integration of the main circuit was very difficult

Method used

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Experimental program
Comparison scheme
Effect test

Embodiment 1

[0074] Refer to the following Figure 1~4 , Embodiment 1 of the semiconductor integrated circuit of the present invention will be described.

[0075] figure 1 is a block diagram of the semiconductor integrated circuit 100 of Embodiment 1, Figure 2-4 It is a block diagram of each of Modifications 1 to 3 of Embodiment 1. First, refer to figure 1 To illustrate the structure and action.

[0076] The semiconductor integrated circuit 100 includes a frequency division ratio setting voltage terminal 101 , an AD (analog to digital) converter 103 , a frequency division ratio setter 104 , a wave detector 105 , a PLL circuit 108 , and a memory 118 . In addition, the AD converter 103, the frequency division ratio setter 104, and the memory 118 constitute a first frequency division ratio setting unit. The wave detector 105, the frequency division ratio setter 104, and the memory 118 constitute a second frequency division ratio setting unit. The PLL circuit 108 is configured to incl...

Embodiment 2

[0093] Below, refer to Figure 5 , 6 Embodiment 2 of the semiconductor integrated circuit of the present invention will be described.

[0094] Figure 5 Shown is a block diagram of the semiconductor integrated circuit 200 of the second embodiment, Figure 6 A modified example of the semiconductor integrated circuit 200 is shown. The structure and operation will be described below. exist Figure 5 , 6 In , the same components as in Embodiment 1 are denoted by the same symbols. In addition, descriptions of the same parts as those in Embodiment 1 will not be repeated.

[0095] Figure 5 and figure 1The difference of the illustrated first embodiment is that a potential is applied from the current source 114 to the frequency division ratio setting voltage terminal 101 via the current mirror circuit 119 . Here, by connecting the resistor 115 between the frequency division ratio setting voltage terminal 101 and the reference potential, the potential at the frequency divisi...

Embodiment 3

[0097] Below, refer to Figure 7 Embodiment 3 of the semiconductor integrated circuit of the present invention will be described.

[0098] Figure 7 Shown is a block diagram of the semiconductor integrated circuit 300 of the third embodiment. Figure 7 In , the same components as in Embodiments 1 and 2 are denoted by the same symbols. In addition, description of the same parts as those in Embodiments 1 and 2 will not be repeated.

[0099] Figure 7 and figure 1 Example 1 shown, and figure 2 The difference of the illustrated embodiment 2 is that a buffer circuit 121 is provided between the frequency division ratio setting voltage terminal 101 and the AD converter 103 . By providing the buffer circuit 121, the following advantages can be obtained in terms of circuit operation.

[0100] When the input terminal impedance of the AD converter 103 drops extremely for some reason (for example, a part of the AD converter 103 fails), the voltage on the frequency division ratio ...

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Abstract

This semiconductor integrated circuit contains: a local oscillator (109) that can perform an oscillation operation at a plurality of frequencies; a reference signal oscillator (107) that oscillates at a predetermined reference frequency; and a variable frequency divider (110) that divides the output signal of the local oscillator by n times the reference frequency. The semiconductor integrated circuit is provided with: a first dividing ratio setting unit (103, 104, 118) that controls the dividing ratio of the variable frequency divider in accordance with a supplied DC potential; and a second dividing ratio setting unit (104, 105, 118) that controls the dividing ratio of the variable frequency divider in accordance with the presence or absence of a supplied pulse signal. By means of the control of the dividing ratio of the variable frequency divider by means of the first dividing ratio setting unit or the second dividing ratio setting unit, the oscillation frequency of the local oscillator is set to a desired frequency, and the DC potential is supplied to the first dividing ratio setting unit via a current mirror circuit (119).

Description

technical field [0001] The present invention relates to a semiconductor integrated circuit including a PLL (PhaseLockedLoop: phase-locked loop) for LNB (LowNoiseBlock-downConverter: low-noise downconverter). Background technique [0002] Figure 9 A satellite broadcast receiving system adopted in Patent Document 1 is shown, and the system includes a conventional LNB 201 mounted on an antenna for satellite broadcast, and a satellite broadcast tuner 301 connected to the LNB 201 . The configuration and operation of the frequency conversion processing in the LNB 201 will be described below. [0003] The LNB 201 includes a mixer 202 for converting the frequency of a broadcast signal from a satellite into a reception frequency of a satellite broadcast tuner, and local oscillators 203 and 204 for oscillating the mixer 202 . [0004] The signal S201 of 10.7GHz-12.75GHz sent from the satellite is converted into the signal S202 of 950MHz-2150MHz by frequency conversion processing of ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03L7/183H04L7/033
CPCH03L7/183
Inventor 满仲健
Owner SHARP KK