Through silicon via (TSV) exposure structure

Abstract

The invention discloses a through silicon via (TSV) exposure structure, which comprises a semiconductor substrate. At least one TSV conductive column is arranged in the semiconductor substrate, penetrates through a part between the front and back surfaces of the substrate, and extends from the back surface of the substrate to form an exposed part. A sloped buffer area is arranged in the connected area of the back surface of the substrate and the exposed part of the TSV, and has a continuous height change. The height of the sloped buffer area is gradually transitioned from a greatest height at a position close to the exposed part of the TSV to a height the same as that of the back surface of the substrate. A buffer structure is arranged between the exposed part of the TSV and the surface of the semiconductor substrate to present the continuous height change between the exposed part of the TSV and the surface of the semiconductor substrate, so that the conventional perpendicular relationship between the exposed part of the TSV and the surface of the semiconductor substrate is changed, the problem that a seed layer is probably faulted at the exposed part of the TSV in a physical vapor deposition (PVD) process is solved, and the reliability of connection between a micro salient point and the exposed part of the TSV is improved.

Description

Technical field [0001] The present invention relates to a process for manufacturing or processing semiconductor or solid devices in the field of microelectronics technology, in particular to a silicon through hole back surface suitable for micro-bump technology that uses metal 3D interconnection to transmit current between separate elements in a microelectronic device Outcrop structure. Background technique [0002] With the continuous advancement of microelectronics technology, the feature size of integrated circuits continues to shrink, and the interconnect density continues to increase. At the same time, users' requirements for high performance and low power consumption continue to increase. In this case, the way to improve performance by further reducing the line width of the interconnect is limited by the physical characteristics of the material and the equipment process. The resistance and capacitance (RC) delay of the two-dimensional interconnect is gradually becoming a l...

AI Technical Summary

Problems solved by technology

However, a height difference greater than 2 microns is a challenge for PVD (Physical Vapor Deposition) technology for depositing a two-dimensional electroplating seed layer in the conventional bump preparation process. It is difficult for existing equipment technology to ensure that the exposed part of the TSV is in a vertical relationship with the silicon substrate. Continuity of the seed layer near the outer wall of the TSV

Especially when ultra-fine-pitch micro-bumps are directly formed on TSVs, because the size of micro-bumps is generally slightly larger than that of TSVs, holes are easily formed at the junction between the silicon substrate and TSVs and the outer wall of TSVs, thereby affecting the interconnection. even reliability

[0004] In the existing patent documents and other technical documents, there is no precedent for improving the technical solutions for the above problems.

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