Flip-chip packaging techniques and configurations

Abstract

Embodiments of the present disclosure flip-chip packaging techniques and configurations. An apparatus may include a package substrate having a plurality of pads formed on the package substrate, the plurality of pads being configured to receive a corresponding plurality of interconnect structures formed on a die and a fluxing underfill material disposed on the package substrate, the fluxing underfill material comprising a fluxing agent configured to facilitate formation of solder bonds between individual interconnect structures of the plurality of interconnect structures and individual pads of the plurality of pads and an epoxy material configured to harden during formation of the solder bonds to mechanically strengthen the solder bonds. Other embodiments may also be described and / or claimed.

Description

technical field [0001] Embodiments of the present disclosure relate generally to the field of integrated circuit packaging, and in particular flip chip packaging techniques and configurations. Background technique [0002] An integrated circuit (IC) package may include various components (eg, die and / or passive components) coupled to a package substrate using solderable materials. For example, solder joints may be formed to electrically and / or mechanically couple components to the packaging substrate. Solder joints may fail (e.g., crack or break) when exposed to elevated temperatures associated with thermal processes (e.g., solder reflow or molding processes) or when subjected to equipment or customer handling . Thermal failures may be due in part to the expansion / contraction rates associated with the various materials of the integrated circuit package. For example, the materials of the die and packaging substrate may have different coefficients of thermal expansion (TCE)...

AI Technical Summary

Problems solved by technology

One or more cleaning operations can add cost and / or time to the manufacturing process used to make the IC package

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