Time measurement method and device
A technology of time measurement and clock, which is applied in the field of computers, can solve the problem of low measurement time accuracy and achieve the effect of improving the signal-to-noise ratio and measurement time accuracy
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Embodiment 1
[0036] see figure 1 , it is the method flowchart of a kind of time measurement method of the present invention, is applied in FPGA (Field-ProgrammableGateArray, Field Programmable Gate Array), and this method comprises setting stage:
[0037] Convert the input clock of the FPGA into N sub-clocks, and the period of each sub-clock is M, where the quotient of M divided by N is the minimum counting unit for time measurement;
[0038] Adjust the phase difference between adjacent sub-clocks to L according to the number N of sub-clocks, where L is the quotient of dividing 360° by N;
[0039] Preferably, the input clock of the FPGA is converted into N sub-clocks, and the period of each sub-clock is M, wherein the quotient of M divided by N is the minimum counting unit for time measurement and is specifically:
[0040] The input clock of FPGA is converted into 20 sub-clocks, and the period of each sub-clock is 2.5ns, wherein, the quotient of dividing the period of each sub-clock of 2....
Embodiment 2
[0062] Corresponding to the above-mentioned time measuring method, an embodiment of the present invention further provides a time measuring device. see image 3 , which is a device structure diagram of a time measuring device according to the present invention, which includes a setting unit 300 , a counting unit 301 and a unit 302 for determining the time of occurrence.
[0063] The setting unit 300 is used to convert the input clock of the FPGA into N sub-clocks, and the period of each sub-clock is M, wherein the quotient of M divided by N is the minimum counting unit for time measurement; according to the number N of the sub-clocks, the phase The phase difference between adjacent sub-clocks is adjusted to L, where L is the quotient of 360° divided by N;
[0064] Preferably, the setting unit is specifically:
[0065] The input clock of FPGA is converted into 20 sub-clocks, and the period of each sub-clock is 2.5ns, wherein, the quotient of dividing the period of each sub-cl...
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