Unlock instant, AI-driven research and patent intelligence for your innovation.

FFT processor based on ieee802.11.ad protocol

A processor and protocol technology, applied in the field of short-distance broadband communication, can solve the problems of unacceptable consumption of hardware resources, consumption of too many multiplier resources, large consumption of hardware resources, etc., achieve continuous work, less hardware resources, and hardware resource consumption little effect

Inactive Publication Date: 2016-08-10
UNIV OF ELECTRONICS SCI & TECH OF CHINA
View PDF3 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The advantage of the memory-based structure is that the hardware resource consumption is small, and its disadvantage is that the throughput rate is small, and the throughput rate is limited by the number of available processors and the bandwidth of the storage device. This structure is not suitable for the IEEE802.11.ad protocol, because if required Achieving a throughput rate of 1.76GSps, the consumption of hardware resources by this structure will be unacceptable; the advantage of the pipeline structure is that the throughput rate is high, and its disadvantage is that the consumption of hardware resources is large, but the simple pipeline structure will consume too many multiplier resources

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • FFT processor based on ieee802.11.ad protocol
  • FFT processor based on ieee802.11.ad protocol
  • FFT processor based on ieee802.11.ad protocol

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0029] Referring to the accompanying drawings, the architecture of the FFT processor will be described in detail below.

[0030]The schematic diagram of the top-level architecture of the FFT processor of the embodiment of the present invention is as follows figure 1 As shown, it specifically includes: a first conjugate unit, a multiplexer unit, a first-level calculation unit, a second-level calculation unit, a third-level calculation unit, a second conjugate unit, a division by 512 unit, and a demultiplexer unit , wherein, the input end of the first conjugation unit and the input end of the multiplexer unit are connected together for inputting 8 parallel input signals, and the output end of the first conjugation unit is connected with the input end of the multiplexer unit; The output end of the multiplexer unit is connected to the input end of the first-level calculation unit, the first-level calculation unit, the second-level calculation unit and the third-level calculation u...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses an FFT / IFFT processor based on the IEEE802.11.ad protocol, which specifically includes: a first conjugation unit, a multiplexer unit, a first-level calculation unit, a second-level calculation unit, and a third-level calculation unit unit, a second conjugate unit, a divide-by-512 unit, and a demultiplexer unit. The FFT processor of the present invention adopts the decomposition method of base 24-22-23 mixed base, so that the complexity of the generated twiddle factor is the lowest, and combined with the pipeline structure, finally the consumption of hardware resources is the least; for the multiplication of the twiddle factor, the CSD coding method is adopted, Therefore, the consumption of the multiplier unit is greatly reduced, it can be applied to the IEEE802.11.ad protocol, supports a throughput rate of 1.76GSps, can work continuously, consumes less hardware resources, and can switch between FFT and IFFT calculations.

Description

technical field [0001] The invention belongs to the technical field of short-distance broadband communication, and in particular relates to the design of an FFT processor. Background technique [0002] IEEE802.11.ad is a standardized protocol for 60GHz short-distance ultra-wideband communication, which can support a transmission rate of several gigabits, and fully meets applications such as high-definition data stream download and high-definition video playback. The protocol has four physical layer modes, one of which uses OFDM (orthogonal frequency division multiplexing) modulation and the other three use single carrier modulation. For OFDM modulation, FFT (Fast Fourier Transform) is one of its core calculations; for single carrier modulation, FFT is widely used in the channel equalization module. It can be seen that the FFT processor is an important part of the communication system based on the IEEE802.11.ad protocol. [0003] The symbol rate of the single carrier mode o...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/14H04L29/06
Inventor 王超严余伟傅晓宇
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA