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On-chip buffering method and device

A cache and register technology, applied in the field of on-chip cache methods and devices, can solve the problems of on-chip cache error-prone and high hardware resource overhead, and achieve the effects of improving operation convenience, accuracy, and speed

Active Publication Date: 2014-01-15
SANECHIPS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] The present invention provides an on-chip cache method and device to at least solve the problems in the related art that the on-chip cache is prone to errors and hardware resources are expensive

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  • On-chip buffering method and device

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Embodiment Construction

[0030] Hereinafter, the present invention will be described in detail with reference to the drawings and examples. It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0031] This embodiment provides an on-chip caching method, wherein the on-chip caching method includes step S102 to step S104.

[0032] Step S102: The pipeline for iterative calculation starts at a preset time slot.

[0033] Step S104: shift and register the iterative variable results of the iteratively calculated pipeline stages in the on-chip buffer according to the preset cycle, wherein the interval of the preset time slot is an integer multiple of the preset cycle.

[0034] Through the above steps, the iterative calculation pipeline is started at the preset time slot, and the iterative calculation results of the iterative variable of each level of the pipeline are shifted and registered in the o...

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Abstract

The invention provides an on-chip buffering method and device. The method includes the steps that pipelines of iterative computations are started at a preset time slot; according to a preset cycle, iteration variable results of all the levels of pipelines of the iterative computations are stored in the on-chip buffering device in a shifting mode, wherein the interval cycle of the preset slot is integral multiples that of the preset cycle. The problems that in the correlation technology, on-chip buffering is prone to generating errors, and expenditure of hardware resources is high are solved, so that accuracy of on-chip buffering is effectively improved, the hardware resources are saved, and meanwhile the speed of the iterative computations is improved.

Description

technical field [0001] The present invention relates to the field of communications, in particular to an on-chip cache method and device. Background technique [0002] In the algorithm design of digital circuits, large-scale iterative calculations are often encountered. In order to save hardware resources, iteration variables are often stored in off-chip storage devices with large fixed delays (for example, QDR storage devices). However, At this time, we will encounter such a problem: For the same group of two iteration operations that are relatively close together, the current iteration calculation needs to use the calculation result of the last iteration variable as the input of the current iteration calculation, and the calculation result of the last iteration variable is still It is too late to read from the off-chip memory or write to the off-chip memory. At this time, if the current iterative calculation adopts the method of reading the off-chip memory to obtain the ca...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38G06F12/08G06F12/0893
Inventor 殷俊杰
Owner SANECHIPS TECH CO LTD