Memory device

Abstract

A memory device includes a parity circuit configured to detect presence or absence of an error using a plurality of command signals and a plurality of address signals, a command shift circuit configured to shift the plurality of command signals by a preset delay value in synchronization with a control clock, a clock control circuit configured to deactivate the control clock when there is no valid command signal in command signals being shifted in the command shift circuit, and a decoder circuit configured to decode a plurality of command signals output from the command shift circuit.

Description

[0001] Cross References to Related Applications

[0002] This application claims priority from Korean Patent Application No. 10-2012-0066004 filed on June 20, 2012, the entire contents of which are hereby incorporated by reference. technical field

[0003] Exemplary embodiments of the present invention relate to a memory device, and more particularly, to a technique for detecting errors of commands and addresses. Background technique

[0004] One of methods for checking errors of transmitted / received data is parity check. The parity check means an error check for setting the number of data having a value '1' in the received multi-bit data to one of even and odd, and checking that the received multi-bit data has a value Whether the data bit of '1' coincides with the even number or the odd number. For example, in the case of an even parity check, if the number of data having a value '1' is even in received multi-bit data, it is judged that there is no error, and if the numbe...

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