Unlock instant, AI-driven research and patent intelligence for your innovation.

CMOS transistors and methods of forming them

A transistor and polysilicon gate technology, applied in the field of CMOS transistors and their formation, to achieve the effects of improving reliability, increasing stability, and avoiding the phenomenon of peering

Active Publication Date: 2017-03-01
SEMICON MFG INT (SHANGHAI) CORP
View PDF4 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The object of the present invention is to provide a kind of CMOS transistor and its formation method, to solve the defect of peeling produced by existing technology

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • CMOS transistors and methods of forming them
  • CMOS transistors and methods of forming them
  • CMOS transistors and methods of forming them

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0044] The CMOS transistor and its forming method provided by the present invention will be further described in detail below with reference to the drawings and specific embodiments. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in a very simplified form, and are only used for the purpose of conveniently and clearly assisting in describing the embodiments of the present invention.

[0045] Please refer to figure 2 , this embodiment provides a method for manufacturing a field effect transistor with a metal gate.

[0046] Specifically, a substrate is provided, and the substrate includes: a P well 20, an N well 21, and a shallow trench isolation 22, and the P well 20 and the N well 21 are arranged on both sides of the shallow trench isolation 22, Both the P well 20 and the N well 21 are formed with source and drain, and the source and drain may be doped with silicon germ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
thicknessaaaaaaaaaa
Login to View More

Abstract

The invention discloses a CMOS transistor and a forming method thereof. A gate metallic layer is subjected to nitrogen injection by the implant process to form a nitride layer; the nitride layer can be well bonded to both the gate metallic layer and a mask layer which is formed later; accordingly, stability of the mask layer is improved greatly, peeling is avoided, and reliability of devices is improved.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to a CMOS transistor and a forming method thereof. Background technique [0002] With the continuous improvement of the existing technology, the industry has gradually transitioned from avoiding the use of CMOS transistors to using CMOS transistors. The formation process of CMOS transistors is usually to first form a sacrificial polysilicon gate, which acts in the initial processing process, and then replaces it with a CMOS transistor, which not only retains the advantages of polysilicon gates, but also has the advantages of metal in electrical properties. [0003] Currently, most CMOS transistors including P-type Metal Oxide Semiconductor Field Effect Transistors (PMOS) and N-type Metal Oxide Semiconductor Field Effect Transistors (NMOS) adopt metal gate structures. figure 1 Shown is a schematic diagram of a CMOS transistor in a prior art process. Described CMOS tr...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8238H01L21/28H01L27/092
CPCH01L21/2822H01L21/823857
Inventor 平延磊周鸣
Owner SEMICON MFG INT (SHANGHAI) CORP
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More