Process compatible decoupling capacitor and manufacturing method

Abstract

The invention provides a process-compatible decoupling capacitor device and a manufacturing method thereof. The decoupling capacitor device includes a first dielectric layer portion deposited in a deposition process that also deposits a second dielectric layer portion for a non-volatile memory cell. Both parts are patterned using a single mask. A system-on-chip (SOC) device is also provided, the SOC includes RRAM cells and decoupling capacitors in a single intermetal dielectric layer. Methods for forming process compatible decoupling capacitors are also provided. The method includes patterning a top electrode layer, an insulating layer, and a bottom electrode layer to form a nonvolatile storage element and a decoupling capacitor.

Description

technical field [0001] The invention relates to the field of semiconductors, and more particularly, to a process-compatible decoupling capacitor and a manufacturing method thereof. Background technique [0002] The semiconductor integrated circuit industry has experienced rapid development over the past few decades. Technological advances in semiconductor materials and design have produced ever smaller and more complex circuits. These advances in materials and designs are made possible as techniques related to processing and fabrication also undergo technological advances. In the course of semiconductor development, the number of interconnected devices per unit area has increased as the smallest feature size that can be reliably manufactured decreases. [0003] Many technological advances in semiconductors have occurred in the area of ​​memory devices, some of which involve capacitors. In addition, capacitors can be used in other applications of integrated circuits (ICs),...

AI Technical Summary

Problems solved by technology

Decoupling capacitors on a particular SOC have not been adequate so far and may create more and more problems in the future

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