Method for manufacturing semiconductor device

Abstract

The present invention provides a method for manufacturing a semiconductor device. The method comprises the steps of providing a semiconductor substrate possessing an NMOS area and a PMOS area, wherein dummy gate structures are formed on the semiconductor substrate; forming a contact hole etching stop layer and a spin-on dielectric layer orderly on the semiconductor substrate; etching back the spin-on dielectric layer until the contact hole etching stop layer at the tops of the dummy gate structures is exposed completely; implementing a post-etch processing process to form an oxide layer on the surface of the spin-on dielectric layer; removing the contact hole etching stop layer at the tops of the dummy gate structures; simultaneously etching the sacrifice gate electrode layers in the dummy gate structures of the NMOS area and the PMOS area to form gate grooves; forming a silicon-containing bottom anti-reflection coating to fill the gate grooves completely; and forming metal gate structures of the NMOS area and the PMOS area respectively. According to the present invention, the reduction in the height of the gates during the formation process of the metal gate structures can be reduced furthest.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a method for forming a metal gate structure. Background technique [0002] In the manufacturing process of next-generation integrated circuits, a high-k-metal gate process is usually used for the fabrication of complementary metal-oxide-semiconductor (CMOS) gates. For transistor structures with higher process nodes, the high-k-metal gate process is usually a gate-last process, and its typical implementation process includes: first, forming a dummy gate on a semiconductor substrate structure, the dummy gate structure is composed of a bottom-up interface layer, a high-k dielectric layer, a cover layer and a sacrificial gate electrode layer; then, a gate spacer structure is formed on both sides of the dummy gate structure , and then removing the sacrificial gate electrode layer of the dummy gate structure, leaving a trench between the gate spacer structures; then, sequential...

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Problems solved by technology

[0003] The above-mentioned process leads to a serious drop in the height of the gate, which will cause the loss of the silicon material of the substrate when the shared contact hole is formed later, and affect the performance of CMOS

There are two reasons for the decrease in the height of the gate: first, after forming the dummy gate structure and the gate spacer structures on both sides, a contact hole etch stop layer and an interlayer are sequentially formed on the semiconductor substrate. Dielectric layer, then implement a grinding process to expose the top of the dummy gate structure, this grinding process will also remove part of the dummy gate structure, thus causing a decrease in gate height; second, due to the CMOS The metal gate structures of the PMOS part and the NMOS part need to have different work functions. Therefore, the metal gate structures of the two are formed separately, and the work function metal is sequentially formed in the trench formed after removing the dummy gate structure. layer, barrier layer, wetting layer and metal gate need to perform two or more grinding processes, these grinding processes will also cause a drop in gate height

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