A Method for Analyzing Correlation of Pipeline Instructions

Abstract

The invention discloses an analysis method for assembly line instruction correlation, and provides a verification method for analyzing minimum instruction sequences from the perspective of user application. Through LEON instruction correlation analysis, correlation verification requirements can be met under the condition that at least three-level instruction correlation is verified. In consideration of protection to function program codes written by users, input files used in the method are 32bit machine codes generated after compiling of the users, and instruction sequences used by the users can be acquired through analysis; correlation of the instruction sequences is analyzed to acquire used and repeatedly used instruction sequence analysis results, instruction correlation verification is guided, and instruction verification is ensured to effectively meet application requirements of the users.

Description

technical field [0001] The invention relates to the technical field of processor instruction verification, and relates to an analysis method for pipeline instruction correlation. Background technique [0002] The LEON processor is an open source microprocessor soft core, including integer hardware multiplication and division units, dual coprocessors (FPU floating point processing unit and coprocessor), separate instruction and data buses. The architecture includes input and output I / O ports, memory management unit, cache sub-architecture system (MMU) and super-privilege software, memory model, etc.; the soft core has very good configurability and portability, in VHDl source code On the basis, a domestically produced SOC system can be established by adding customized computing units and peripheral interfaces in combination with specific needs. The processor contains 172 commonly used instructions and 40-520 registers. The instruction set is very complex, so large-scale instr...

AI Technical Summary

Problems solved by technology

The correlation between SPARC V8 instructions and registers is very complicated. Assuming that an instruction can use 10 kinds of register combinations, there are (172*10) possible correlations in the five-stage pipeline. 5 , plus the different formats of each instruction, there may be more instruction sequences. It is impossible to complete the verification method by traversing all instruction sequences relying on the current verification conditions, so the comprehensiveness and effectiveness of the verification cannot be guaranteed.

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