Method and device for generating jump time delay fault vector

Abstract

The invention provides a jump change time delay fault vector generation method and device. The method includes the steps that a first enabling flip-flop is determined, and the first enabling flip-flop is used for controlling a source end flip-flop of a time exception path; jump change time delay fault vectors are screened out of test vectors randomly generated, and the jump change time delay fault vectors enable the first enabling flip-flop to scan a level value at the end of a shift to be of an invalid state. Therefore, when the jump change time delay fault vectors are applied in the test process, the time exception path is not triggered, the phenomenon that the measuring result alternatively succeeds and fails in the prior art is avoided, accuracy of the test and stability of the jump change time delay fault vectors are improved, analysis of the time exception path in the process of generating the jump change time delay fault vectors in the prior art is not needed, and the complexity of the ATPG tool for generating the jump change time delay fault vectors is reduced.

Description

technical field [0001] The invention relates to the technical field of testing, in particular to a method and device for generating a jump time delay fault vector. Background technique [0002] Chips are affected by factors such as manufacturing process and manufacturing materials during the manufacturing process, which will inevitably bring some defects. Therefore, it is necessary to test the chips to exclude chips with defects. At present, the chip can be tested by using the transition delay fault model, that is, using the Automatic Test Pattern Generation (ATPG) tool to generate a test vector according to the transition delay fault model, and then using the test vector to test the chip. Each path of the path is tested, that is, the test vector makes the source end of the path start a jump on one clock edge, and when the impact of this jump on the terminal of the path is captured on the next clock edge, the test chip is normal, otherwise the test Chip failure. Since the ...

AI Technical Summary

Problems solved by technology

[0004] However, in the prior art, if there are multiple time exception paths sharing the same terminal trigger, although no "X" value is detected on the terminal trigger during the process of generating the test vector, it means that the test vector will not cause The terminal trigger jumps, but in the actual test process, due to the different delays of each time exception path, there is a possibility that the terminal trigger jumps, which will cause the test results to sometimes succeed and sometimes fail, thereby reducing stability of the test vector

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