[0030] The first embodiment, a method for writing memory, such as figure 2 Shown, including:
[0031] Input the instruction to write the buffer to clear the data in the buffer;
[0032] Write the addresses of N units in the memory and the programmed data corresponding to each address into the buffer; where N is a positive integer;
[0033] According to the programming data in the buffer, the N units are checked and programmed in parallel; wherein, the programming of any unit refers to: writing the programming data corresponding to the address of the unit in the buffer into the unit.
[0034] In an implementation of this embodiment, N is 64 or 128.
[0035] This implementation mode can write 64bits or 128bits data at a time; take the situation of writing 128bit data as an example, change the circuit from one word line to 8 or 16 bit lines to one word line to connect 128 bits line. If the pump's drive strength (strength) is not enough to support programs with 64 bits and above, you can increase the pump clk (clock) frequency and pump capacitance to enhance the pump's drive ability to meet the 64 or 128 bit current requirements. It is possible to program at the same time.
[0036] The existing verify process only targets one word, and the existing program process only targets 8 or 16 bit operations. In the method of this embodiment, during the program process, multiple writing data of multiple addresses are sent at the same time, and they are temporarily stored in the buffer, and then multiple bit lines (64bits or 128bits) can be operated, that is, they can be operated at the same time. Verifying 64bits or 128bits data greatly reduces the verification time, and can program 64bits or 128bits data at the same time, and the data needed in the process of verify and program is loaded from the buffer, without every time Input, save time; although the program time for 128bits at the same time is longer than that for 16bits, the average program time on one bit is greatly reduced, which improves the efficiency of writing. It is equivalent to the verify process can be increased to verify 4 words or 8 words, and in the original program time of one word, 4 words or 8 words can be programmed. This greatly improves the efficiency of verify and program.
[0037] In an implementation manner of this embodiment, before the step of inputting the write buffer instruction, it may further include:
[0038] When an error occurs in the data in one or more addresses, reload the one or more addresses and the programmed data of the one or more addresses into the buffer;
[0039] After all data is confirmed to be correct, the step of inputting the instruction of the write buffer is executed.
[0040] In this embodiment, the wrong data can be modified into correct data without erasing. In the existing scheme, in some continuous writing process, if you write wrong data to an address, if you want to correct it, you can only erase this block and then write the correct data; In the writing process of the write buffer, load data is required first, allowing multiple loads of data to an address, and writing in the last data, thereby reducing more write times.
[0041] In an implementation manner of this embodiment, the step of verifying and writing the N units in parallel may specifically include:
[0042] S1. Compare each programmed data in the buffer with the data in the unit at the corresponding address of the programmed data, and obtain N comparison results corresponding to the addresses of the N units; when the programmed data is the same as the data in the unit At the same time, or when the unit has been programmed, the comparison result is 1;
[0043] S2. Use the N comparison results as the programmed data corresponding to the address to overwrite the original programmed data in the buffer; determine whether the programmed data in the buffer are all 1; if yes, end; if not, then Write each programmed data of 0 in the buffer into the unit at the corresponding address of the programmed data, and return to step S1.
[0044] The following uses a 4-bit unit distance to illustrate the above steps, assuming that the written data in the buffer is:
[0045] 0011;
[0046] The data in the cell at the corresponding address is:
[0047] 0101;
[0048] When verifying for the first time, the comparison result is:
[0049] 1011;
[0050] Among them, the first and fourth bits are because the programmed data in the buffer is the same as the data in the unit, so the comparison result is "1"; and the data in the third bit is "0", so the unit is programmed For the cell, the comparison result is also 1 (the programmed cell is in the real state, and it is the MOS tube whose threshold has been raised. It cannot be changed to the "1" state except through the erase operation).
[0051] Load the comparison result into the buffer to overwrite the original programmed data; because the programmed data in the buffer is not all "1", at this time all "0" in the program, that is, the second bit unit is programmed, and the programmed data is "0".
[0052] The data in the cell at the corresponding address after program is:
[0053] 0001;
[0054] Then perform a second verify, that is, compare again; the comparison result (previously written data in the buffer has been updated to "1011") is:
[0055] 1111;
[0056] Among them, the data in the unit of bits 1, 2, and 3 is 0, so the comparison result is "1"; and the 4th bit is because the data written in the buffer is the same as the data in the unit, so the comparison result is also "1" .
[0057] Write the comparison result back into the buffer to replace the original programmed data; at this time, all data in the buffer are "1", and the process of verification and programming is completed.
[0058] If the programming of the second cell is not successful, and the data in the real cell is still "0101" at the beginning, the comparison result is still "1011" during the second verify (buffer is "1011", and the fourth The bit data is the same, so the comparison result is "1", and the data in the first and third bit units is "0", so the comparison result is "1"). Write "1011" back into the buffer. Since it is still not all "1", the second unit will continue to be programmed. It can be seen that until the writing is successful, that is, the data in the unit is "0001", the situation that the data written in the buffer is "1111" will be obtained, and the verification and writing will end.
[0059] Parallel verification and programming of 64-bit or 128-bit units can be deduced by analogy.
