Afterimage elimination device, display and afterimage elimination method

Abstract

The invention relates to an afterimage elimination device comprising a multistage grid circuit and a grid electrode driving module; the multistage grid circuit is used for outputting a modulated grid electrode opening voltage according to an enable signal; the grid electrode driving module receives the modulated grid electrode opening voltage outputted by the multistage grid circuit, and provides the opening voltage to grid electrode lines in different layers. Technical change in a panel end is not needed, an afterimage elimination time is short, and a grid electrode signal and a fall time thereof are controllable, so an afterimage elimination effect is controllable, and flexibility is good.

Description

technical field [0001] The invention relates to the display field of mobile phones, in particular to a device for eliminating afterimages, a display device and a method for eliminating afterimages. Background technique [0002] At present, in order to achieve narrow borders, Half-size Video Graphics Array (HVGA) products generally adopt a double-layer wiring design, such as figure 1 As shown, since gate signal lines such as G1, G3, G5, G7, and G9 use gate layer metal transmission, gate signal lines such as G2, G4, G6, and G8 use source-drain metal transmission, but when double-layer wiring The resistance difference between the two layers of metal involved is large, and due to the influence of factors such as film formation uniformity, the gate signal delay difference between the gate layer and the source-drain layer in the two layers of metal is relatively large, especially Far away from the back end of the panel of the integrated circuit, the delay of the gate signal will ...

AI Technical Summary

Problems solved by technology

[0002] At present, in order to achieve narrow borders, Half-size Video Graphics Array (HVGA) products generally adopt a double-layer wiring design, such as figure 1 As shown, since gate signal lines such as G1, G3, G5, G7, and G9 use gate layer metal transmission, gate signal lines such as G2, G4, G6, and G8 use source-drain metal transmission, but when double-layer wiring The resistance difference between the two layers of metal involved is large, and due to the influence of factors such as film formation uniformity, the gate signal delay difference between the gate layer and the source-drain layer in the two layers of metal is relatively large, especially Far away from the back end of the panel of the integrated circuit, the delay of the gate signal will affect the feed-through voltage ΔVp, thereby affecting the pixel voltage and resulting in differences, resulting in afterimages in gray-scale images with alternating light and dark

To solve this problem, the process change can only be done through the panel side at present, but the change verification cycle is long, and the change of process may also exacerbate the above problems

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