A Design Method of High Speed and Variable Frame Video Memory Based on FPGA
A design method and variable technology, applied in the direction of standard conversion, etc., to achieve the effect of flexible data interface and stable dynamic balance
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[0025] The embodiments of the present invention are described in detail below. This embodiment is implemented on the premise of the technical solution of the present invention, and detailed implementation methods and specific operating procedures are provided, but the protection scope of the present invention is not limited to the following implementation example.
[0026] See figure 1 , figure 2 , a kind of FPGA-based high-speed, variable frame video memory design method provided by the present embodiment comprises the following steps:
[0027] A. Use the field programmable logic device FPGA to connect the video source and the screen. The PFGA is equipped with a DDR memory, a DDR controller controlling the DDR memory, and a front-end asynchronous FIFO and a back-end asynchronous connection respectively connected to the input and output ends of the DDR memory. FIFOs;
[0028] B. The video source starts to send the video source data, and at the same time performs the DDR me...
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