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A Design Method of High Speed ​​and Variable Frame Video Memory Based on FPGA

A design method and variable technology, applied in the direction of standard conversion, etc., to achieve the effect of flexible data interface and stable dynamic balance

Active Publication Date: 2017-06-06
AVIC HUADONG OPTOELECTRONICS (SHANGHAI) CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

With the rapid development of electronic technology, the functions of display devices are becoming more and more diversified, and the amount of information transmitted is also increasing. The previous video memory design schemes are difficult to meet the diverse functional requirements of today, and FPGA with its high-speed , flexible design, just cater to this kind of development needs

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  • A Design Method of High Speed ​​and Variable Frame Video Memory Based on FPGA
  • A Design Method of High Speed ​​and Variable Frame Video Memory Based on FPGA

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Embodiment Construction

[0025] The embodiments of the present invention are described in detail below. This embodiment is implemented on the premise of the technical solution of the present invention, and detailed implementation methods and specific operating procedures are provided, but the protection scope of the present invention is not limited to the following implementation example.

[0026] See figure 1 , figure 2 , a kind of FPGA-based high-speed, variable frame video memory design method provided by the present embodiment comprises the following steps:

[0027] A. Use the field programmable logic device FPGA to connect the video source and the screen. The PFGA is equipped with a DDR memory, a DDR controller controlling the DDR memory, and a front-end asynchronous FIFO and a back-end asynchronous connection respectively connected to the input and output ends of the DDR memory. FIFOs;

[0028] B. The video source starts to send the video source data, and at the same time performs the DDR me...

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Abstract

The invention discloses an FPGA (Field Programmable Gate Array) high-speed variable-frame video memory design method. The method comprises the following steps: starting to send video source data through a video source end; initializing a DDR (Double Data Rate) storage; receiving the data through the front-end asynchronous FIFO (First In First Out); writing the data of the front-end asynchronous FIFO in the DDR storage while the data size cached by the front-end asynchronous FIFO reaches a threshold; reading data to a rear-end asynchronous FIFO through the DDR storage while the data stored in the DDR storage reaches a frame; starting a dot-screen module to send the data into a screen while the data size in the rear-end asynchronous FIFO reaches the threshold, wherein the storage address space in the DDR storage is divided into three areas according to the size of a single-frame image, wherein the three areas are respectively marked as A, B and C; operating a DDR controller to control the read-write operation of the DDR storage to be alternatively performed once among the areas A, B and C. The method has the advantages that various video signals can be flexibly processed, like caching, efficient transmission and frame varying.

Description

technical field [0001] The invention relates to an FPGA-based high-speed, variable-frame video memory design method. Background technique [0002] Field programmable logic device FPGA has been widely used in various engineering designs with its high-speed processing speed and flexible design methods, and DDR memory, as a functional module under the FPGA platform, makes it in video Great progress has been made in video memory solutions. With the rapid development of electronic technology, the functions of display devices are becoming more and more diversified, and the amount of information transmitted is also increasing. The previous video memory design schemes are difficult to meet the diverse functional requirements of today, and FPGA with its high-speed , flexible design, is catering to this development needs. Contents of the invention [0003] The purpose of the present invention is to overcome the deficiencies in the prior art, providing a kind of FPGA-based high-spe...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04N7/01
Inventor 王杰徐涵
Owner AVIC HUADONG OPTOELECTRONICS (SHANGHAI) CO LTD