Device for controlling data stream and buffering frame of video processing chip

Abstract

The invention provides a device for controlling data stream and buffering frame of a video processing chip, comprising an input buffer pool for receiving and buffering an external data stream, an output buffer pool for realizing the output of the processed data stream, and a control module for performing a real-time control on the input and output of the data stream, performing a read-write control on a frame buffer, and performing a conversion on the video frame rate of the data stream. The input buffer pool is in an on-chip connection with an OSD (on-screen display) control module and a video input processing module; the output buffer pool is in an on-chip connection with a video output processing module; and the control module is in an off-chip connection with the frame buffer. A plurality of FIFO (first input first output) structure asynchronous buffers are included in the input buffer pool and the output buffer pool; the control module comprises an arbitration module, an address management module and a video memory controller; the arbitration module is composed of a finite state converter, for realizing a real-time control on the data stream input and output of each path by utilizing a direct jumping policy and a priority dynamic adjusting policy; the video memory controller utilizes a burst transmission method; and the frame buffer utilizes a SDRAM (synchronous dynamic random access memory) or DDR SDRAM (double data rate synchronous dynamic random access memory).

Description

technical field [0001] The present invention relates to a data flow control and frame buffer device, in particular, to a video processing chip, which realizes real-time control of input / output of multiple data streams and control of reading and writing of frame buffers, and realizes video frame Video processing chip data flow control and frame buffer device with rate conversion function. Background technique [0002] In DTV, HDTV real-time video post-processing chips, it is necessary to process a large amount of video signal data and on-screen display (OSD) data in real time. For example, for a standard-definition video signal of 720*57650Hz, a data throughput rate greater than 300Mb / s needs to be processed, and the data volume of one frame of image is greater than 800K bytes. In addition, data is often not a single channel, but multi-channel signal input / output coexists. For example, in a typical application, there are OSD signals and three video signals of Y, U, and V. ...

AI Technical Summary

Problems solved by technology

[0005] There is another problem with using off-chip SDRAM as the frame buffer: there is only one input and output port of SDRAM, but there are more than one set of data streams processed by the chip.

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