A multi-channel packet timer
A timer and multi-channel technology, applied in multiplexing communication, time division multiplexing system, electrical components, etc., can solve the problem of consuming large logic resources, achieve consistent timing arrival time, and simple timing arrival judgment Effect
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Embodiment 1
[0019] This embodiment adopts the FPGA of model 5CEFA4F23C8N, provides a kind of multi-channel grouping timer and comprises, comprises reading and writing control module (by FPGA logic control realization), storage module (by the RAM block realization in FPGA), timing judgment module (by FPGA logic control) and accumulation module (realized by FPGA logic control), wherein, the read-write control module is connected with the storage module, the storage module is connected with the timing judgment module, and the timing judgment module is connected with the The accumulating module is connected, the accumulating module is connected with the read-write control module, and the timing judging module also includes a timing output port.
[0020] The read-write control module is used to control the reading and writing of the timing count data of the storage module; the storage module is used to store the timing count data; the timing judging module is used to store timing configuration ...
Embodiment 2
[0038] In some embodiments, the timer includes 3 storage modules, and each storage module includes 512 registers, and each register is a timing channel. It can realize timing control for 512 communication channels at the same time, and each channel can set 3 different levels of timing (different time), timing step = clock period of the read-write control module * 3 * 512.
Embodiment 3
[0040] In some embodiments, the timer includes 10 storage modules, each of which contains 256 registers, and each register is a timing channel, which can realize timing control of 256 communication channels at the same time, and each communication channel can be set to 10 Timing of different levels (different time), timing step = clock period of the read-write control module*3*256.
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