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A multi-channel packet timer

A timer and multi-channel technology, applied in multiplexing communication, time division multiplexing system, electrical components, etc., can solve the problem of consuming large logic resources, achieve consistent timing arrival time, and simple timing arrival judgment Effect

Active Publication Date: 2017-02-01
CHENGDU LONGRAISE TECH DEV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If the counter method is used to implement a multi-channel multi-period timer, it needs to consume a lot of logic resources

Method used

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  • A multi-channel packet timer

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Experimental program
Comparison scheme
Effect test

Embodiment 1

[0019] This embodiment adopts the FPGA of model 5CEFA4F23C8N, provides a kind of multi-channel grouping timer and comprises, comprises reading and writing control module (by FPGA logic control realization), storage module (by the RAM block realization in FPGA), timing judgment module (by FPGA logic control) and accumulation module (realized by FPGA logic control), wherein, the read-write control module is connected with the storage module, the storage module is connected with the timing judgment module, and the timing judgment module is connected with the The accumulating module is connected, the accumulating module is connected with the read-write control module, and the timing judging module also includes a timing output port.

[0020] The read-write control module is used to control the reading and writing of the timing count data of the storage module; the storage module is used to store the timing count data; the timing judging module is used to store timing configuration ...

Embodiment 2

[0038] In some embodiments, the timer includes 3 storage modules, and each storage module includes 512 registers, and each register is a timing channel. It can realize timing control for 512 communication channels at the same time, and each channel can set 3 different levels of timing (different time), timing step = clock period of the read-write control module * 3 * 512.

Embodiment 3

[0040] In some embodiments, the timer includes 10 storage modules, each of which contains 256 registers, and each register is a timing channel, which can realize timing control of 256 communication channels at the same time, and each communication channel can be set to 10 Timing of different levels (different time), timing step = clock period of the read-write control module*3*256.

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Abstract

The invention relates to the field of network communication timing, in particular to a multi-channel grouping timer. The multi-channel grouping timer comprises a read-write control module, a storage module for storing timing count data, a timing judgment module for storing timing configuration data and judging whether the timing count data reach the timing configuration data and an accumulation module for adding one to the timing count data or conducting zero clearing on the timing count data. According to the multi-channel grouping timer, several sets of memorizers with the same channel number are used as timers, all channels in each memorizer have the same preset time, and different memorizers have different kinds of preset time; timing is achieved through periodic read-write by the read-write control module to the storage module, so that a counter is not needed, the timing arrival time of the timers in each set is consistent, and the multi-channel grouping timer is simple in timing arrival judgment and practical.

Description

technical field [0001] The invention relates to the field of network communication timing, in particular to a multi-channel grouping timer. Background technique [0002] In the field of communication, a large number of timers are often required to complete multi-channel timeout alarms. For example, timeout statistics are performed on multi-channel received messages. If the message is not received within the specified timing period, a receive timeout alarm will be issued; there may be several types of receive timeout for the same channel. For example, if the timeout is 3.3ms, alarm 1 will be issued. When the timeout is 10ms, alarm 2 is issued, when the timeout is 100ms, alarm 3 is issued, etc., different levels of timeout alarms output different alarm pulses, and the corresponding level of alarm processing is performed. In a communication system, sometimes hundreds of channels need to be timed, and most of the timing cycle levels are only a few. If the counter method is use...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04J3/06
Inventor 胡强刘雁行许鹏
Owner CHENGDU LONGRAISE TECH DEV