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[Delta][sigma] modulator and [delta][sigma] A/D converter

A technology of modulator and integrator, which is applied in the field of ΔΣ modulator and ΔΣ type A/D converter, which can solve the problem of alleviating the driving ability of the operational amplifier and achieve the effect of high-speed sampling frequency

Inactive Publication Date: 2014-12-24
TOYOTA JIDOSHA KK
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the above structure, if the sampling capacitor of the first stage and the sampling capacitor of the second stage are alternately connected to the operational amplifier of the integrator of the first stage without simultaneous connection of two sampling capacitors to the above integrator, the operational amplifier The settling time constant in the integral action and the settling time constant in the lower sampling action are equalized, so the drive capability of the operational amplifier is eased

Method used

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  • [Delta][sigma] modulator and [delta][sigma] A/D converter
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  • [Delta][sigma] modulator and [delta][sigma] A/D converter

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Embodiment 1

[0046] figure 1 An overall configuration diagram of a ΔΣ-type A / D converter 12 including a ΔΣ modulator 10 according to the first embodiment of the present invention is shown. The ΔΣ-type A / D converter 12 of this embodiment is an analog-to-digital conversion device that converts an input analog input signal into digital data using the ΔΣ modulator 10 . The ΔΣ-type A / D converter 12 is used for sensor detection, motor / solenoid current detection, load short-circuit / open-circuit detection, etc. used in, for example, vehicle electronic control.

[0047] Such as figure 1 As shown, the ΔΣ-type A / D converter 12 includes a ΔΣ modulator 10 provided in the preceding stage, and a digital filter 14 provided in the subsequent stage. An analog input signal is input to the ΔΣ modulator 10 . The ΔΣ modulator 10 converts the input analog input signal into a digital signal sequence quantized by predetermined bits, and outputs the sequence. An input of a digital filter 14 is connected to th...

Embodiment 2

[0103] In the first embodiment described above, the integrator (passive integrator) 18_2 at the final stage of the ΔΣ modulator 10 is constituted by a single-ended circuit. On the other hand, in the second embodiment of the present invention, the final-stage integrator (passive integrator) is constituted by a fully differential circuit in which both the input and the output are of a differential configuration.

[0104] Generally, in an active SC integrator of a ΔΣ modulator, if in the integration phase If the gain of the operational amplifier is sufficiently high, the differential input ((Vi-)-(Vi+)) of the operational amplifier becomes approximately zero after stable operation, and almost all of the charge accumulated in the sampling capacitor Cs is transferred to the integrating capacitor Cf , so the active SC integrator becomes an ideal integrator with almost no integrator leakage.

[0105] On the other hand, in a passive integrator, during the integration phase In this...

Embodiment 3

[0160] However, in the ΔΣ type A / D converter, when a DC value around a certain rational number (u=x / y) is applied as the analog input potential Vin, the ΔΣ modulator outputs a periodic sequence, which may cause Unexpected periodic signal (idle tone). Regarding this idle tone, in particular, simple rational numbers such as "0", "1 / 2", and "1 / 3" are applied to the analog input potential Vin in the primary and secondary relatively low-order ΔΣ modulators. DC values ​​in the vicinity of Ω are prone to occur, and are prone to occur in passive integrators with integrator leakage. If the idle tone has a frequency component included in the signal frequency band of the analog input potential Vin, the idle tone cannot be removed in the digital filter at the next stage of the ΔΣ modulator, resulting in a signal-to-noise ratio (SNR; Signal-to- NoiseRatio) deterioration and other characteristics decreased.

[0161] In a ΔΣ-type A / D converter with a passive integrator installed in the fin...

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Abstract

The present invention relates to a [delta][sigma] modulator and a [delta][sigma] A / D converter, wherein, with a simple configuration, by accelerating a settling time constant of a final stage integrator, a sampling frequency of a [delta][sigma] modulator overall is accelerated. Specifically, provided is a [delta][sigma] modulator comprising a plurality of integrators which are cascade connected, wherein the integrator which is located in the final stage is a passive integrator which does not employ an amplifier circuit, and the integrators which are located in the second to last or earlier stages are active SC integrators which employ the amplifier circuit and a switch capacitor circuit. Additionally, each integrator respectively carries out an integration computation by alternately repeating a first operation phase of sampling an input signal and charging a sampling capacitor, and a second phase of transferring to an integration capacitor the charge with which the sampling capacitor is charged and integrating same.

Description

technical field [0001] The present invention relates to a ΔΣ modulator and a ΔΣ-type A / D converter, and more particularly to a ΔΣ modulator in which a plurality of integrators are connected in cascade and a ΔΣ-type A / D converter using the ΔΣ modulator. Background technique [0002] Conventionally, a ΔΣ-type A / D converter is known as a high-resolution A / D conversion method (for example, refer to Patent Document 1). The ΔΣ type A / D converter includes a ΔΣ modulator provided in the preceding stage and a digital filter provided in the subsequent stage. The ΔΣ modulator converts an analog input signal into an output value (digital signal sequence) quantized by 1 bit or several coarse bits, and outputs the output value. In addition, the digital filter removes quantization error components from the digital signal sequence which is the output signal of the ΔΣ modulator, and performs final digital output. [0003] The ΔΣ modulator has: a differential signal generator that generates...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M3/02
CPCH03M3/374H03M3/39H03M3/416H03M3/424H03M3/454H03M3/422H03M3/458H03M3/464
Inventor 渡边光
Owner TOYOTA JIDOSHA KK