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Test structure for monitoring performance of dielectric layers

A technology for testing structures and dielectric layers, applied in semiconductor/solid-state device testing/measurement, electrical components, circuits, etc., can solve problems such as improving monitoring efficiency, unfavorable performance monitoring, etc., and achieve the effect of improving monitoring efficiency

Inactive Publication Date: 2015-01-14
WUHAN XINXIN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] It can be seen from the above that several test structures in the prior art can only monitor the dielectric layer of the same layer or the dielectric layer between layers, but cannot simultaneously monitor the dielectric layer of the same layer and the dielectric layer between different layers. Layer (such as interlayer dielectric layer) performance is monitored, which is not conducive to improving monitoring efficiency

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  • Test structure for monitoring performance of dielectric layers
  • Test structure for monitoring performance of dielectric layers
  • Test structure for monitoring performance of dielectric layers

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Embodiment Construction

[0022] The test structure for monitoring the performance of the medium layer of the present invention will be described in more detail below in conjunction with the schematic diagram, wherein a preferred embodiment of the present invention is represented, it should be understood that those skilled in the art can modify the present invention described here, and still realize the present invention beneficial effect. Therefore, the following description should be understood as the broad knowledge of those skilled in the art, but not as a limitation of the present invention.

[0023] In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions and constructions are not described in detail since they would obscure the invention with unnecessary detail. It should be appreciated that in the development of any actual embodiment, numerous implementation details must be worked out to achieve the developer's s...

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Abstract

The invention provides a test structure for monitoring the performance of dielectric layers. A first metal connecting wire and a second metal connecting wire which are staggered and arranged in a comb shape are formed in the dielectric layer between first metal layers, a third metal connecting wire and a fourth metal connecting wire which are staggered and arranged in a comb shape are formed in the dielectric layer between second metal layers, a dielectric interlayer is formed between the dielectric layer between the first metal layers and the dielectric layer between the second metal layers, the first metal connecting wire is connected with the fourth metal connecting wire through through hole connecting wires, and the second metal connecting wire and the third metal connecting wire are connected through through hole connecting wires. By monitoring the leakage current between the first metal connecting wire and the second metal connecting wire, the performance of the same dielectric layer and different dielectric layers can be monitored, and the monitoring efficiency is improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a test structure for monitoring the performance of a dielectric layer. Background technique [0002] In the semiconductor manufacturing process, the dielectric layer plays the role of isolating different devices and different metal connections. As the integration of semiconductor devices becomes higher and higher, the performance requirements for the dielectric layer become more and more stringent. The quality of the dielectric layer can often affect the yield of the entire chip. In order to be able to monitor the performance of the formed dielectric layer, the following test structures are usually used for monitoring in the prior art. [0003] Please refer to Figure 1a and Figure 1b , Figure 1a and Figure 1b is the first test structure in the prior art, wherein, Figure 1b is along Figure 1a A schematic cross-sectional view in the middle AA' direction, the fir...

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Application Information

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IPC IPC(8): H01L21/66
CPCH01L22/30
Inventor 罗旖旎苏捷峰张宇飞
Owner WUHAN XINXIN SEMICON MFG CO LTD