FPGA (field programmable gate array)-based failure recovery method

Abstract

The invention discloses an FPGA (field programmable gate array)-based failure recovery method. The FPGA-based failure recovery method can be used for monitoring the working condition of an FPGA after power on; if the phenomenon that logic loading fails or breaks down and the like occurs, the logic is reset by a hardware watchdog; if software embedded into the FPGA is loaded unsuccessfully or breaks down, the software is reset through logic software so as to realize failure recovery of the module, and moreover, operations, such as burning and configuration, on the FPGA are not influenced. The method is suitable for the conditions that failure recovery is needed, so that the work reliability is improved; moreover, the method has a general function, and can be suitable for various Xilinx FPGA-based failure recovery conditions.

Description

technical field [0001] The invention relates to a fault recovery method based on FPGA. Background technique [0002] Xilinx's FPGA chip is a volatile device based on SRAM technology, and the circuit function is realized by data stored in SRAM configuration registers. After the FPGA chip is powered on, it must read the configuration information from the configuration FLASH before it can work normally. [0003] The FPGA configuration process includes 5 stages: initialization, clearing the configuration memory, loading configuration data, CRC check, START-UP, the power-on sequence of the configuration process is as follows figure 1 As shown, when the chip is powered on or the PROG_B signal of the FPGA is a low pulse, the configuration register will be cleared, that is, the configuration information will be read from the configuration FLASH again. The shortest pulse time of PROG_B is determined by T POR The time parameter determines that when the signal is valid (low level), ...

AI Technical Summary

Problems solved by technology

[0004] The existing FPGA is not equipped with a working status monitoring system. If an abnormal phenomenon occurs, it cannot be reset in time, and it also affects the programming and configuration of the FPGA.

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