Code type data, apparatus and test method for automatically testing chip MDIO bus protocol

A technology of automatic testing and bus protocol, applied in the direction of single semiconductor device testing, etc., can solve the problems of low degree of automation of testing tools, consumption of testing ability of engineering personnel, low test coverage, etc., to save testing time, get rid of human influence, Improve overall effect

Inactive Publication Date: 2015-03-11
CHIPSEA TECH SHENZHEN CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Due to the lack of good test tools, the chip MDIO interface is generally neglected in the industry. After the chip is manufactured, if the MDIO interface can be controlled to communicate with other MAC or PHY devices, it is assumed that the design of the MDIO interface meets the requirements. Specific parameters such as the maximum and minimum rates supported by the MDIO bus, the minimum setup time for receiving and sending data, the minimum tolerable pulse width for high and low clock levels, the filtering capability of data signals, and the impact of data not transmitted according to standards, etc. have not been tested.
When the chip reaches the end customer, various problems occur frequently. Therefore, the test coverage rate of the MDIO interface protocol of the chip is low in the current public information in the industry, and the automation degree of the test tool is low, which has a relatively high test ability for the engineering personnel. require and take a long time

Method used

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  • Code type data, apparatus and test method for automatically testing chip MDIO bus protocol
  • Code type data, apparatus and test method for automatically testing chip MDIO bus protocol
  • Code type data, apparatus and test method for automatically testing chip MDIO bus protocol

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Embodiment Construction

[0032] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0033] Please refer to figure 1 , figure 2 and image 3 , Figure 4 As shown, the specific implementation ideas of the present invention are as follows: a master device and a corresponding slave device are actually involved when the MDIO bus works, in order to test the slave device PHY and the master device MAC, when testing the slave device PHY, the present invention simulates Master device MAC manages slave device PHY, when testing master device MAC, the present invention simulates slave device PHY and responds to master device MAC, so be divided into from module and master module below (mast...

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Abstract

The invention discloses code type data, an apparatus and a test method for automatically testing a chip MDIO bus protocol. The code type data is 32-bit Bit data, each Bit data comprises three portions, each portion is corresponding to the level of MDC and MDIO and corresponding duration, and each portion employs a 32-bit data format. The apparatus and the test method, through the structural form of the data, can completely unify MDIO tests, automatically test a device PHY and a master device MAC, and find out problems of chips in design more rapidly and accurately.

Description

technical field [0001] The invention belongs to the field of chip testing, in particular to a testing chip data format and testing method based on the MDIO bus protocol. Background technique [0002] In the production process of the chip, a necessary process is to test. At present, there are various testing methods in the testing process. For example, patent application 201310445372.0 discloses a chip testing device and method based on FPGA. The application includes a host computer, The FPGA board and the board to be tested are characterized in that the FPGA board is connected to the host computer via the USB bus, and the FPGA board is connected to the board to be tested, wherein the board to be tested is provided with a chip packaging socket, including DIPs connected to the FPGA board respectively. Package sockets, SSOP package sockets, QFP package sockets, and SOP package sockets, this patent application can realize rapid detection of logic functions of multiple chips, is ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/26
Inventor 方学南
Owner CHIPSEA TECH SHENZHEN CO LTD
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